Diverse Lynx
Title: Implementation, Physical Design Senior Engineer
Location: Cupertino, CA
Duration: Fulltime
Job Description
Must Have Technical/Functional Skills
• Technical Skills: Complete ownership on Place and Route (PNR) implementation (Floorplanning, Placement, CTS, post_route, etc.) on latest nodes. Signoff knowledge is mandatory (STA, Power analysis, FV, Low power verification, Physical Verification). Quick learner with good analytical and problem-solving skills. Define Implementation requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle. Discussions with 3rd party IP providers, foundry partners and design services. End to end tasks from flow development to sign-off. Deploy innovative techniques for improving power, performance and area (PPA) of the design, drive experiments with RTL, and evaluate synthesis, timing and power results. Proficiency in RTL to GDS flows and methodologies, with significant experience in advanced nodes (7nm, 5nm, 3nm or below). Working knowledge of scripting languages (Perl, TCL, AWK, Python).
• Collaboration: Collaborating with cross-functional teams (e.g., design, simulation, process engineers) to ensure design meets requirements.
• Simulation and Verification: Performing simulations to verify design performance, including timing, power, and signal integrity.
Diverse Lynx LLC is an Equal Employment Opportunity employer. All qualified applicants will receive due consideration for employment without any discrimination. All applicants will be evaluated solely on the basis of their ability, competence and their proven capability to perform the functions outlined in the corresponding role. We promote and support a diverse workforce across all levels in the company.
Location: Cupertino, CA
Duration: Fulltime
Job Description
Must Have Technical/Functional Skills
• Technical Skills: Complete ownership on Place and Route (PNR) implementation (Floorplanning, Placement, CTS, post_route, etc.) on latest nodes. Signoff knowledge is mandatory (STA, Power analysis, FV, Low power verification, Physical Verification). Quick learner with good analytical and problem-solving skills. Define Implementation requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle. Discussions with 3rd party IP providers, foundry partners and design services. End to end tasks from flow development to sign-off. Deploy innovative techniques for improving power, performance and area (PPA) of the design, drive experiments with RTL, and evaluate synthesis, timing and power results. Proficiency in RTL to GDS flows and methodologies, with significant experience in advanced nodes (7nm, 5nm, 3nm or below). Working knowledge of scripting languages (Perl, TCL, AWK, Python).
• Collaboration: Collaborating with cross-functional teams (e.g., design, simulation, process engineers) to ensure design meets requirements.
• Simulation and Verification: Performing simulations to verify design performance, including timing, power, and signal integrity.
Diverse Lynx LLC is an Equal Employment Opportunity employer. All qualified applicants will receive due consideration for employment without any discrimination. All applicants will be evaluated solely on the basis of their ability, competence and their proven capability to perform the functions outlined in the corresponding role. We promote and support a diverse workforce across all levels in the company.