Meta Platforms
Digital Design Engineer, Reality Labs Silicon AI Research
Meta Platforms, Sunnyvale, California, United States, 94086
Digital Design Engineer, Reality Labs Silicon AI Research
We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and integrate advanced IP and AI accelerators into SOC/ASIC solutions to enable in-system testing and prototyping. The goal is to de-risk new IP/accelerators, prove out advanced compute/memory architectures and to harden controls/algorithms for next generation AI and Augmented Reality solutions. As a Digital Design Engineer (DDE), you will be a key contributor in planning and executing our front-end and back-end digital design efforts at the IP and sub-system levels. From microarchitecture definition and RTL implementation to synthesis and timing closure, fundamentals in digital design will enable you to contribute to all phases of the chip development. Additionally, effective collaboration and communication with Digital Design Engineers, Digital Verification Engineers, Research Scientists and Cross Functional Partner teams will be key to your success. Responsibilities
Contribute to microarchitectural feature definition, RTL design, design verification and project planning Deliver quality RTL in collaboration with Digital Verification Support back end physical design (PD) through STA and SDCs Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads Help create and maintain design documentation including IP/SoC Micro Architecture document (collaborator/owner), IP/SoC Design plan (collaborator) and SoC/chip bringup/validation plan (collaborator) Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience in digital design, hardware engineering or related experience Communication and collaboration skills Knowledge of digital SoC integration and ASIC architecture Skilled in micro-architecture, RTL coding, design verification and SoC Integration of complex IPs Experience in CDC, SDC and STA Self directed and detail oriented in all phases of digital design Preferred Qualifications
Experience in DFT/Testability requirement definition and understanding of test program development Python, or similar scripting experience Familiarity with low-power design techniques Experience using C for system verification Master's degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience Some familiarity with compute and/or memory architectures for ultra low power applications Knowledge of common industry interfaces like AXI, APB, I3C, SPI, UART, etc Familiar with IP, sub-system and SoC Design Verification to execute Design Verification working with DV lead
We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and integrate advanced IP and AI accelerators into SOC/ASIC solutions to enable in-system testing and prototyping. The goal is to de-risk new IP/accelerators, prove out advanced compute/memory architectures and to harden controls/algorithms for next generation AI and Augmented Reality solutions. As a Digital Design Engineer (DDE), you will be a key contributor in planning and executing our front-end and back-end digital design efforts at the IP and sub-system levels. From microarchitecture definition and RTL implementation to synthesis and timing closure, fundamentals in digital design will enable you to contribute to all phases of the chip development. Additionally, effective collaboration and communication with Digital Design Engineers, Digital Verification Engineers, Research Scientists and Cross Functional Partner teams will be key to your success. Responsibilities
Contribute to microarchitectural feature definition, RTL design, design verification and project planning Deliver quality RTL in collaboration with Digital Verification Support back end physical design (PD) through STA and SDCs Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads Help create and maintain design documentation including IP/SoC Micro Architecture document (collaborator/owner), IP/SoC Design plan (collaborator) and SoC/chip bringup/validation plan (collaborator) Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience in digital design, hardware engineering or related experience Communication and collaboration skills Knowledge of digital SoC integration and ASIC architecture Skilled in micro-architecture, RTL coding, design verification and SoC Integration of complex IPs Experience in CDC, SDC and STA Self directed and detail oriented in all phases of digital design Preferred Qualifications
Experience in DFT/Testability requirement definition and understanding of test program development Python, or similar scripting experience Familiarity with low-power design techniques Experience using C for system verification Master's degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience Some familiarity with compute and/or memory architectures for ultra low power applications Knowledge of common industry interfaces like AXI, APB, I3C, SPI, UART, etc Familiar with IP, sub-system and SoC Design Verification to execute Design Verification working with DV lead