Altera
Memory Controller Lead Design Engineer
Altera - San Jose, California, United States, 95112
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Overview
Memory Controller Lead Design Engineer
Join Altera, a pioneer in programmable logic solutions, where innovation meets practicality. We empower system, semiconductor, and technology companies to rapidly and cost-effectively differentiate and excel in their markets. Our legacy of innovation is matched by our commitment to our clients, whom we serve through a robust distribution network and a dedicated sales force. Our portfolio spans programmable logic products, acceleration platforms, software, and IP, all designed to accelerate the pace of innovation. About the Role We are seeking an experienced Memory Controller Lead Design Engineer to join our team. The ideal candidate will bring experience in the integration of memory controller IPs, with a strong background in DDR and LPDDR memory technologies. This role requires expertise in the entire integration process, including RTL coding, performance analysis, synthesis, and timing closure. Key Responsibilities Lead the integration of DDR and LPDDR memory controller IPs. Collaborate with cross-functional teams to define and implement memory controller features and enhancements. Develop and optimize RTL code for memory controllers. Performance analysis, synthesis, and timing closure to ensure high-quality and reliable memory controller designs. Provide technical leadership and mentorship to junior engineers. Stay updated with the latest advancements in memory technologies and industry trends. Design and implement memory controller features such as memory encryption, DFI, and AXI protocols. Integrate and perform memory calibration techniques. Develop and maintain high-level architectural specifications for memory controllers. Optimize memory controller performance, power, and area (PPA) metrics. Collaborate with firmware and software teams to ensure seamless integration of memory controller features. Collaborate with silicon validation team on post-silicon validation plan and debug regarding memory controller features and memory interface. Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $178.9k - $259.0k USD #LI-KM1 Qualifications 10+ years of total experience in memory controller IP integration & development and expertise in DDR and LPDDR memory technologies. Proficiency in RTL coding using Verilog or VHDL. Strong understanding of memory controller architecture and design principles. Experience with performance analysis, synthesis, and timing closure methodologies. Excellent problem-solving and analytical skills. Strong communication and leadership abilities. Ways to Stand Out From the Crowd Experience with memory encryption, DFI, and AXI protocols. Knowledge of PHY integration and memory calibration techniques. Familiarity with simulation and emulation tools. Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Join Altera, a pioneer in programmable logic solutions, where innovation meets practicality. We empower system, semiconductor, and technology companies to rapidly and cost-effectively differentiate and excel in their markets. Our legacy of innovation is matched by our commitment to our clients, whom we serve through a robust distribution network and a dedicated sales force. Our portfolio spans programmable logic products, acceleration platforms, software, and IP, all designed to accelerate the pace of innovation. About the Role We are seeking an experienced Memory Controller Lead Design Engineer to join our team. The ideal candidate will bring experience in the integration of memory controller IPs, with a strong background in DDR and LPDDR memory technologies. This role requires expertise in the entire integration process, including RTL coding, performance analysis, synthesis, and timing closure. Key Responsibilities Lead the integration of DDR and LPDDR memory controller IPs. Collaborate with cross-functional teams to define and implement memory controller features and enhancements. Develop and optimize RTL code for memory controllers. Performance analysis, synthesis, and timing closure to ensure high-quality and reliable memory controller designs. Provide technical leadership and mentorship to junior engineers. Stay updated with the latest advancements in memory technologies and industry trends. Design and implement memory controller features such as memory encryption, DFI, and AXI protocols. Integrate and perform memory calibration techniques. Develop and maintain high-level architectural specifications for memory controllers. Optimize memory controller performance, power, and area (PPA) metrics. Collaborate with firmware and software teams to ensure seamless integration of memory controller features. Collaborate with silicon validation team on post-silicon validation plan and debug regarding memory controller features and memory interface. Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $178.9k - $259.0k USD #LI-KM1 Qualifications 10+ years of total experience in memory controller IP integration & development and expertise in DDR and LPDDR memory technologies. Proficiency in RTL coding using Verilog or VHDL. Strong understanding of memory controller architecture and design principles. Experience with performance analysis, synthesis, and timing closure methodologies. Excellent problem-solving and analytical skills. Strong communication and leadership abilities. Ways to Stand Out From the Crowd Experience with memory encryption, DFI, and AXI protocols. Knowledge of PHY integration and memory calibration techniques. Familiarity with simulation and emulation tools. Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.