Claros Technologies™ Inc.
Digital Design Engineer
Claros Technologies™ Inc. - California, Missouri, United States, 65018
Work at Claros Technologies™ Inc.
Overview
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Overview
Claros is a power management solutions company that is innovating at the intersection of power andcompute to make AI more sustainable and widely available. By driving down the cost and complexity of power deliveryand leveraging innovative hardware and software, the company seeks to decrease energy consumption, optimizepower delivery, increase compute performance, and maximize the efficiency of AI operations.
About Claros
Claros innovates at the intersection of power and compute. We build advanced semiconductor power management solutions that improve AI compute capacity, efficiency and reliability.Claros is an early-stage startup company located in Torrance, CA. If you are looking for challenging work and a strong technical environment with the collaborative & supportive culture, then Claros Tech is the company for you. We offer industry the best competitive pay & benefits and early-stage stock options.
Location:
Minimum of 3 days a week in the office in Torrance, CA.(Hybrid role) About the Team We are open-minded, fast paced, problem solvers that value open dialogue and candor. Our passion is to challenge the status-quo and we embrace transformational thinking. Our response is never “no, but….” instead “yes, if….”. We are mindful of our personal and organizational blinders and try to build an environment where are team members are At Their Best. About The Role We are seeking a motivated and detail-oriented
Digital Design Engineer
to join our team in the development of digitally controlled power management integrated circuits (PMICs). The ideal candidate will have a strong foundation in ASIC design methodologies, with hands-on experience in timing closure, design optimization, and functional verification. This role spans the full lifecycle of PMIC digital design from RTL development and simulation through post-silicon validation using FPGA platforms. What You Will Do Design and implement digital blocks within PMICs using Verilog/SystemVerilog and standard ASIC design flows. Participate in pre-silicon simulation and verification using Cadence tools and standard cell libraries. Support ASIC tape-out activities, including synthesis, static timing analysis, and design signoff. After silicon returns from the foundry, focus on developing FPGA-based test builds (using Xilinx tools) to validate and characterize fabricated PMIC silicon. Interface and integrate digital control logic with analog/mixed-signal blocks commonly found in power management applications. Write and maintain automation scripts for regression testing, build flows, and hardware validation. Collaborate with cross-functional teams including analog designers, layout, validation, and test engineers to ensure robust and reliable PMIC design. What You Bring B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field. Minimum 2-3 years of experience in the field. Experience with RTL coding using SystemVerilog Experience debugging hardware in a lab environment using benchtop equipment: oscilloscopes, waveform generators, power supplies, logic analyzers Solid understanding of ASIC design flows including RTL design, synthesis, timing closure, and verification. Experience with digital simulation tools (e.g., Xcelium, Questa, Vivado Simulator). Experience with FPGA development using Xilinx tools (Vivado, ISE) for prototyping and silicon validation. Proficient in scripting (Python, TCL, Perl) for automation and test. Strong digital design fundamentals and hardware debugging skills. Excellent analytical and debugging skills Effective communication and documentation habits Proactive, detail-oriented, and committed to high-quality work Comfortable working in cross-functional teams and fast-paced environments What Is Helpful Experience with post-silicon validation and debug of PMICs or mixed-signal ICs. Familiarity with standard cell libraries and digital integration in mixed-signal environments. Knowledge of digital control systems for power regulation, sequencing, or monitoring. Familiarity with Cadence digital implementation tools (Genus, Innovus, Conformal). Experience in hardware/software co-design and test automation. What We Offer Career track opportunity with potential for rapid advancement with strong performance as the firm grows. 100% employer paid, comprehensive health care including medical, dental, and vision for you and your family. Paid maternity and paternity for 14 weeks at employees' normal pay. Unlimited PTO, with management approval. Opportunities for professional development and continued learning. Optional 401K, FSA, and equity incentives available. Salary Range : $135,000-$155,000. This represents the typical salary range for this position based on experience, skills, and other factors. Create a Job Alert Interested in building your career at Claros? Get future opportunities sent straight to your email. Apply for this job
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Minimum of 3 days a week in the office in Torrance, CA.(Hybrid role) About the Team We are open-minded, fast paced, problem solvers that value open dialogue and candor. Our passion is to challenge the status-quo and we embrace transformational thinking. Our response is never “no, but….” instead “yes, if….”. We are mindful of our personal and organizational blinders and try to build an environment where are team members are At Their Best. About The Role We are seeking a motivated and detail-oriented
Digital Design Engineer
to join our team in the development of digitally controlled power management integrated circuits (PMICs). The ideal candidate will have a strong foundation in ASIC design methodologies, with hands-on experience in timing closure, design optimization, and functional verification. This role spans the full lifecycle of PMIC digital design from RTL development and simulation through post-silicon validation using FPGA platforms. What You Will Do Design and implement digital blocks within PMICs using Verilog/SystemVerilog and standard ASIC design flows. Participate in pre-silicon simulation and verification using Cadence tools and standard cell libraries. Support ASIC tape-out activities, including synthesis, static timing analysis, and design signoff. After silicon returns from the foundry, focus on developing FPGA-based test builds (using Xilinx tools) to validate and characterize fabricated PMIC silicon. Interface and integrate digital control logic with analog/mixed-signal blocks commonly found in power management applications. Write and maintain automation scripts for regression testing, build flows, and hardware validation. Collaborate with cross-functional teams including analog designers, layout, validation, and test engineers to ensure robust and reliable PMIC design. What You Bring B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field. Minimum 2-3 years of experience in the field. Experience with RTL coding using SystemVerilog Experience debugging hardware in a lab environment using benchtop equipment: oscilloscopes, waveform generators, power supplies, logic analyzers Solid understanding of ASIC design flows including RTL design, synthesis, timing closure, and verification. Experience with digital simulation tools (e.g., Xcelium, Questa, Vivado Simulator). Experience with FPGA development using Xilinx tools (Vivado, ISE) for prototyping and silicon validation. Proficient in scripting (Python, TCL, Perl) for automation and test. Strong digital design fundamentals and hardware debugging skills. Excellent analytical and debugging skills Effective communication and documentation habits Proactive, detail-oriented, and committed to high-quality work Comfortable working in cross-functional teams and fast-paced environments What Is Helpful Experience with post-silicon validation and debug of PMICs or mixed-signal ICs. Familiarity with standard cell libraries and digital integration in mixed-signal environments. Knowledge of digital control systems for power regulation, sequencing, or monitoring. Familiarity with Cadence digital implementation tools (Genus, Innovus, Conformal). Experience in hardware/software co-design and test automation. What We Offer Career track opportunity with potential for rapid advancement with strong performance as the firm grows. 100% employer paid, comprehensive health care including medical, dental, and vision for you and your family. Paid maternity and paternity for 14 weeks at employees' normal pay. Unlimited PTO, with management approval. Opportunities for professional development and continued learning. Optional 401K, FSA, and equity incentives available. Salary Range : $135,000-$155,000. This represents the typical salary range for this position based on experience, skills, and other factors. Create a Job Alert Interested in building your career at Claros? Get future opportunities sent straight to your email. Apply for this job
indicates a required field First Name * Last Name * Preferred First Name Email * Phone Resume/CV Enter manually Accepted file types: pdf, doc, docx, txt, rtf Enter manually Accepted file types: pdf, doc, docx, txt, rtf
#J-18808-Ljbffr