MIPS
EDA, CAD Engineer
MIPS - San Jose, California, United States, 95199
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Overview
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EDA, CAD Engineer
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EDA, CAD Engineer
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MIPS About Us
We`re a fast-growing CPU IP team building next-generation chips for Physical AI, Networking, and custom compute platforms. We`re lean, highly technical, and focused on accelerating innovation across all levels of the design stack. If you`re passionate about automation, infrastructure, and silicon scalability, you`ll thrive here. About Us
We`re a fast-growing CPU IP team building next-generation chips for Physical AI, Networking, and custom compute platforms. We`re lean, highly technical, and focused on accelerating innovation across all levels of the design stack. If you`re passionate about automation, infrastructure, and silicon scalability, you`ll thrive here.
About The Role
We are looking for an experienced EDA, CAD Engineer to own and scale our front-end design automation flows and CI/CO infrastructure. This role sits at the intersection of digital design, tools engineering, and devops—supporting the full RTL lifecycle from code check-in to synthesis readiness. You`ll work directly with RTL and verification engineers to improve developer velocity and flow robustness.
Key Responsibilities
Design, implement, and maintain automation flows for simulation, regression, and code coverage RTL parameterization, configuration, linting, and synthesis Batch job execution and compute load balancing (using LSF, RDMA, or equivalents) Build and manage our CI/CO infrastructure Automate RTL check-in flows using Git Integrate sanity checks, lint, and regression triggers into the CI pipeline Ensure traceability, consistency, and reporting from check-in to test coverage Collaborate with design and verification engineers to continuously improve usability and efficiency of flow tools Develop internal tools and scripts in Python, Perl, Ruby, or similar Own flow documentation, monitoring, and debugging infrastructure
Minimum Qualifications
10+ years of experience in EDA, CAD engineering, front-end flows, or RTL automation Strong scripting experience (Python, Perl, Ruby, Bash) Coding experience in C or C++ Deep UNIX/Linux expertise, including shell programming, sed, awk and regular expression mastery Experience automating flows using job schedulers (e.g., LSF, RDMA, SLURM) Proficiency with Git and experience managing automated Jira flows triggered by source control activity B.S. or higher in Computer Science, Electrical Engineering, or related field
Preferred Qualifications
Familiarity with RTL design and verification workflows Familiarity with System Verilog and UVM Experience with CI tools like Jenkins, GitLab CI, or GitHub Actions Exposure to EDA toolchains (Synopsys, Cadence, Siemens) Database development Understanding of modern digital design methodology from spec to tape-out
What You`ll Get
A seat at the table in a small, high-impact team Opportunity to build and scale automation infrastructure from scratch Competitive salary + stock grants Flexible hours and remote-friendly culture A dynamic work environment that values speed, autonomy, and engineering excellence
Ready to build the future of silicon automation? Apply now and join a team where your work will directly impact product and process. Seniority level
Seniority level Executive Employment type
Employment type Full-time Job function
Job function Engineering and Information Technology Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at MIPS by 2x Get notified about new Computer Aided Design Engineer jobs in
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EDA, CAD Engineer
role at
MIPS 1 day ago Be among the first 25 applicants Join to apply for the
EDA, CAD Engineer
role at
MIPS About Us
We`re a fast-growing CPU IP team building next-generation chips for Physical AI, Networking, and custom compute platforms. We`re lean, highly technical, and focused on accelerating innovation across all levels of the design stack. If you`re passionate about automation, infrastructure, and silicon scalability, you`ll thrive here. About Us
We`re a fast-growing CPU IP team building next-generation chips for Physical AI, Networking, and custom compute platforms. We`re lean, highly technical, and focused on accelerating innovation across all levels of the design stack. If you`re passionate about automation, infrastructure, and silicon scalability, you`ll thrive here.
About The Role
We are looking for an experienced EDA, CAD Engineer to own and scale our front-end design automation flows and CI/CO infrastructure. This role sits at the intersection of digital design, tools engineering, and devops—supporting the full RTL lifecycle from code check-in to synthesis readiness. You`ll work directly with RTL and verification engineers to improve developer velocity and flow robustness.
Key Responsibilities
Design, implement, and maintain automation flows for simulation, regression, and code coverage RTL parameterization, configuration, linting, and synthesis Batch job execution and compute load balancing (using LSF, RDMA, or equivalents) Build and manage our CI/CO infrastructure Automate RTL check-in flows using Git Integrate sanity checks, lint, and regression triggers into the CI pipeline Ensure traceability, consistency, and reporting from check-in to test coverage Collaborate with design and verification engineers to continuously improve usability and efficiency of flow tools Develop internal tools and scripts in Python, Perl, Ruby, or similar Own flow documentation, monitoring, and debugging infrastructure
Minimum Qualifications
10+ years of experience in EDA, CAD engineering, front-end flows, or RTL automation Strong scripting experience (Python, Perl, Ruby, Bash) Coding experience in C or C++ Deep UNIX/Linux expertise, including shell programming, sed, awk and regular expression mastery Experience automating flows using job schedulers (e.g., LSF, RDMA, SLURM) Proficiency with Git and experience managing automated Jira flows triggered by source control activity B.S. or higher in Computer Science, Electrical Engineering, or related field
Preferred Qualifications
Familiarity with RTL design and verification workflows Familiarity with System Verilog and UVM Experience with CI tools like Jenkins, GitLab CI, or GitHub Actions Exposure to EDA toolchains (Synopsys, Cadence, Siemens) Database development Understanding of modern digital design methodology from spec to tape-out
What You`ll Get
A seat at the table in a small, high-impact team Opportunity to build and scale automation infrastructure from scratch Competitive salary + stock grants Flexible hours and remote-friendly culture A dynamic work environment that values speed, autonomy, and engineering excellence
Ready to build the future of silicon automation? Apply now and join a team where your work will directly impact product and process. Seniority level
Seniority level Executive Employment type
Employment type Full-time Job function
Job function Engineering and Information Technology Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at MIPS by 2x Get notified about new Computer Aided Design Engineer jobs in
San Jose, CA . Mountain View, CA $145,000.00-$170,000.00 2 weeks ago Software Engineer, AI Platform - New Grad
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Mountain View, CA $141,000.00-$202,000.00 1 week ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr