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Senior Verification Engineer
ZipRecruiter - Suwanee, Georgia, United States, 30174
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Job DescriptionJob Description Senior Verification Engineer Also open to staff, principal, or senior principal level engineers! Location:
Suwanee, GA 30024 | Relocation assistance provided in form of a sign-on bonus Hybrid Remote:
3 days in the office per week |
Reporting To:
Sr. Director, Engineering Responsibilities: DDR5 DIMM system-level verification and PMIC IP verification Collaborating with component testing verification teams across global offices Interacting with design, product, and spec engineering teams internally Contributing to silicon debugging as needed Developing, driving, and implementing UVM SystemVerilog TestBench infrastructure Developing stimulus covering, SV assertions, and scripts as necessary Providing mentorship to junior engineers on the team Debugging regressions and failing simulations Requirements: 5+ years of experience in verification engineering in the semiconductor industry Understanding of CMOS circuit design and experience building UVM Testbench from scratch Strong understanding of DDR5 protocol or CXL 2.0 specifications Experience with digital and analog simulation tools: VCS, Xcellieum, Verdi Compensation: $150K - $225K + Annual Bonus + Stock Options
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Suwanee, GA 30024 | Relocation assistance provided in form of a sign-on bonus Hybrid Remote:
3 days in the office per week |
Reporting To:
Sr. Director, Engineering Responsibilities: DDR5 DIMM system-level verification and PMIC IP verification Collaborating with component testing verification teams across global offices Interacting with design, product, and spec engineering teams internally Contributing to silicon debugging as needed Developing, driving, and implementing UVM SystemVerilog TestBench infrastructure Developing stimulus covering, SV assertions, and scripts as necessary Providing mentorship to junior engineers on the team Debugging regressions and failing simulations Requirements: 5+ years of experience in verification engineering in the semiconductor industry Understanding of CMOS circuit design and experience building UVM Testbench from scratch Strong understanding of DDR5 protocol or CXL 2.0 specifications Experience with digital and analog simulation tools: VCS, Xcellieum, Verdi Compensation: $150K - $225K + Annual Bonus + Stock Options
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