Groq
Sr. Staff Formal Verification Engineer
Groq - Palo Alto, California, United States, 94306
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Sr. Staff Formal Verification Engineer
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Groq 1 week ago Be among the first 25 applicants Join to apply for the
Sr. Staff Formal Verification Engineer
role at
Groq About Groq
Apply (by clicking the relevant button) after checking through all the related job information below.
Groq delivers fast, efficient AI inference. Our LPU-based system powers GroqCloud, giving businesses and developers the speed and scale they need. Headquartered in Silicon Valley, we are on a mission to make high performance AI compute more accessible and affordable. When real-time AI is within reach, anything is possible. Build fast. Sr. Staff ASIC Formal Verification Engineer
Mission:
This position will focus on formal verification of Groq’s next generation hardware. Through this work term, the successful candidate will work alongside experienced engineers to help verify complex digital designs using formal verification techniques and tools. You will be involved in tasks ranging from setting up formal verification environments, running automated checks, debugging formal proofs, and supporting the integration of formal verification tools into the overall verification flow .
Verify hardware features of Language Process Unit (LPU). Cross-functional Collaboration: Partner with architecture/RTL teams to specify properties, resolve deep design issues, and influence micro-architecture decisions. Leverage and unleash the power of formal verification to rigorously verify critical design properties and ensure compliance with specifications, as well as minimize spec ambiguities. Debug findings and collaborate with stakeholders in an efficient manner. Support silicon bring-up and debug using formal methods where it applies. Methodology Leadership: Develop and implement advanced formal verification environments and methodologies for complex ASIC designs, including automated flows for scalability and efficiency. Mentorship: Train and coach junior engineers on formal techniques and best practices; Help on methodology/FAQ documentation. Innovate. Contribute to developing future verification strategies for validating future accelerator chips and hardware architectures for ML workloads.
About Groq
Groq delivers fast, efficient AI inference. Our LPU-based system powers GroqCloud, giving businesses and developers the speed and scale they need. Headquartered in Silicon Valley, we are on a mission to make high performance AI compute more accessible and affordable. When real-time AI is within reach, anything is possible. Build fast.
Sr. Staff ASIC Formal Verification Engineer
Mission:
This position will focus on formal verification of Groq’s next generation hardware. Through this work term, the successful candidate will work alongside experienced engineers to help verify complex digital designs using formal verification techniques and tools. You will be involved in tasks ranging from setting up formal verification environments, running automated checks, debugging formal proofs, and supporting the integration of formal verification tools into the overall verification flow .
Responsibilities & opportunities in this role:
Verify hardware features of Language Process Unit (LPU). Cross-functional Collaboration: Partner with architecture/RTL teams to specify properties, resolve deep design issues, and influence micro-architecture decisions. Formal verification execution:
Leverage and unleash the power of formal verification to rigorously verify critical design properties and ensure compliance with specifications, as well as minimize spec ambiguities. Debug findings and collaborate with stakeholders in an efficient manner. Support silicon bring-up and debug using formal methods where it applies.
Methodology Leadership: Develop and implement advanced formal verification environments and methodologies for complex ASIC designs, including automated flows for scalability and efficiency. Mentorship: Train and coach junior engineers on formal techniques and best practices; Help on methodology/FAQ documentation. Innovate. Contribute to developing future verification strategies for validating future accelerator chips and hardware architectures for ML workloads.
Ideal candidates have/are:
Required Qualifications:
BS degree in electrical engineering, or related fields, or equivalent practical experience; advance degrees (MS or PhD) is a plus 10+ years in ASIC verification with 5+ years focused on formal verification methods Mastery of SystemVerilog Assertions (SVA) and formal property verification Proficient on at least one popular formal verification tools in the industry(JapserGold, VC Formal, etc.) Strong analytical skills and attention to detail when debugging complex issues Good scripting skills for flow automation(tcl, python, etc.) Good written and oral communication skills Must be authorized to work in the United States or Canada
Preferred Qualifications:
Proven success in full-cycle formal sign-off for complex compute blocks Expertise in formal apps: sequential equivalence checks, datapath, connectivity, etc. Deep understanding of LPU or GPU architecture/design
Attributes of a Groqster:
Humility - Egos are checked at the door Collaborative & Team Savvy - We make up the smartest person in the room, together Growth & Giver Mindset - Learn it all versus know it all, we share knowledge generously Curious & Innovative - Take a creative approach to projects, problems, and design Passion, Grit, & Boldness - no limit thinking, fueling informed risk taking
If this sounds like you, we’d love to hear from you!
Compensation:
At Groq, a competitive base salary is part of our comprehensive compensation package, which includes equity and benefits. For this role, the base salary range is $206,000 - $290,000, determined by your skills, qualifications, experience and internal benchmarks.
Location:
Some roles may require being located near or on our primary sites, as indicated in the job description.
At Groq:
Our goal is to hire and promote an exceptional workforce as diverse as the global populations we serve. Groq is an equal opportunity employer committed to diversity, inclusion, and belonging in all aspects of our organization. We value and celebrate diversity in thought, beliefs, talent, expression, and backgrounds. We know that our individual differences make us better.
Groq is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans.
Groq is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: talent@groq.com. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodations will be determined on a case-by-case basis.Seniority level
Seniority levelMid-Senior level Employment type
Employment typeFull-time Job function
Job functionQuality Assurance IndustriesSemiconductor Manufacturing Referrals increase your chances of interviewing at Groq by 2x Sign in to set job alerts for “Senior Validation Engineer” roles.Computer Systems Validation, Senior ManagerSenior Quality Engineer (Design Controls and V&V) Sunnyvale, CA $126,100.00-$213,500.00 2 days ago Senior System Power Validation and Applications EngineerSenior Quality Engineer (Design Control and Risk Management) Sunnyvale, CA $126,100.00-$213,500.00 2 days ago Senior Quality Engineer (Design Control & Risk Management) Sunnyvale, CA $126,100.00-$213,500.00 2 days ago Santa Clara, CA $118,000.00-$160,000.00 2 months ago Quality Assurance Quality Control EngineerSenior Software Quality Engineer, Post MarketSenior Software Quality and Compliance Engineer - AD/ADAS SystemsSenior Software Quality Engineer (Non-Product) Alameda, CA $98,000.00-$196,000.00 1 month ago Senior Systems Engineer, Fleet Validation LeadSr Electrical Quality Engineer (Electromechanical) Alameda, CA $125,000.00-$175,000.00 1 month ago Sr Principal Engineer Quality - R10200424 Sunnyvale, CA $124,900.00-$187,300.00 2 days ago Validation Engineering Manager - SerDes, PCIe San Jose, CA $200,000.00-$270,000.00 1 week ago Manager, Systems Verification & Validation, Platform Safety Assurance Foster City, CA $189,000.00-$238,000.00 3 weeks ago Mountain View, CA $202,350.00-$303,050.00 10 hours ago Sr Principal Engineer Quality - Sunnyvale CA Sunnyvale, CA $124,900.00-$187,300.00 1 day ago Client Development Lead, Validation and Regulatory ComplianceSr. Software Engineer, HIL Automation, AutonomySenior Software Engineer, ASIC Verification ToolsSr. Software Engineer, Supply Chain Applications We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
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Sr. Staff Formal Verification Engineer
role at
Groq 1 week ago Be among the first 25 applicants Join to apply for the
Sr. Staff Formal Verification Engineer
role at
Groq About Groq
Apply (by clicking the relevant button) after checking through all the related job information below.
Groq delivers fast, efficient AI inference. Our LPU-based system powers GroqCloud, giving businesses and developers the speed and scale they need. Headquartered in Silicon Valley, we are on a mission to make high performance AI compute more accessible and affordable. When real-time AI is within reach, anything is possible. Build fast. Sr. Staff ASIC Formal Verification Engineer
Mission:
This position will focus on formal verification of Groq’s next generation hardware. Through this work term, the successful candidate will work alongside experienced engineers to help verify complex digital designs using formal verification techniques and tools. You will be involved in tasks ranging from setting up formal verification environments, running automated checks, debugging formal proofs, and supporting the integration of formal verification tools into the overall verification flow .
Verify hardware features of Language Process Unit (LPU). Cross-functional Collaboration: Partner with architecture/RTL teams to specify properties, resolve deep design issues, and influence micro-architecture decisions. Leverage and unleash the power of formal verification to rigorously verify critical design properties and ensure compliance with specifications, as well as minimize spec ambiguities. Debug findings and collaborate with stakeholders in an efficient manner. Support silicon bring-up and debug using formal methods where it applies. Methodology Leadership: Develop and implement advanced formal verification environments and methodologies for complex ASIC designs, including automated flows for scalability and efficiency. Mentorship: Train and coach junior engineers on formal techniques and best practices; Help on methodology/FAQ documentation. Innovate. Contribute to developing future verification strategies for validating future accelerator chips and hardware architectures for ML workloads.
About Groq
Groq delivers fast, efficient AI inference. Our LPU-based system powers GroqCloud, giving businesses and developers the speed and scale they need. Headquartered in Silicon Valley, we are on a mission to make high performance AI compute more accessible and affordable. When real-time AI is within reach, anything is possible. Build fast.
Sr. Staff ASIC Formal Verification Engineer
Mission:
This position will focus on formal verification of Groq’s next generation hardware. Through this work term, the successful candidate will work alongside experienced engineers to help verify complex digital designs using formal verification techniques and tools. You will be involved in tasks ranging from setting up formal verification environments, running automated checks, debugging formal proofs, and supporting the integration of formal verification tools into the overall verification flow .
Responsibilities & opportunities in this role:
Verify hardware features of Language Process Unit (LPU). Cross-functional Collaboration: Partner with architecture/RTL teams to specify properties, resolve deep design issues, and influence micro-architecture decisions. Formal verification execution:
Leverage and unleash the power of formal verification to rigorously verify critical design properties and ensure compliance with specifications, as well as minimize spec ambiguities. Debug findings and collaborate with stakeholders in an efficient manner. Support silicon bring-up and debug using formal methods where it applies.
Methodology Leadership: Develop and implement advanced formal verification environments and methodologies for complex ASIC designs, including automated flows for scalability and efficiency. Mentorship: Train and coach junior engineers on formal techniques and best practices; Help on methodology/FAQ documentation. Innovate. Contribute to developing future verification strategies for validating future accelerator chips and hardware architectures for ML workloads.
Ideal candidates have/are:
Required Qualifications:
BS degree in electrical engineering, or related fields, or equivalent practical experience; advance degrees (MS or PhD) is a plus 10+ years in ASIC verification with 5+ years focused on formal verification methods Mastery of SystemVerilog Assertions (SVA) and formal property verification Proficient on at least one popular formal verification tools in the industry(JapserGold, VC Formal, etc.) Strong analytical skills and attention to detail when debugging complex issues Good scripting skills for flow automation(tcl, python, etc.) Good written and oral communication skills Must be authorized to work in the United States or Canada
Preferred Qualifications:
Proven success in full-cycle formal sign-off for complex compute blocks Expertise in formal apps: sequential equivalence checks, datapath, connectivity, etc. Deep understanding of LPU or GPU architecture/design
Attributes of a Groqster:
Humility - Egos are checked at the door Collaborative & Team Savvy - We make up the smartest person in the room, together Growth & Giver Mindset - Learn it all versus know it all, we share knowledge generously Curious & Innovative - Take a creative approach to projects, problems, and design Passion, Grit, & Boldness - no limit thinking, fueling informed risk taking
If this sounds like you, we’d love to hear from you!
Compensation:
At Groq, a competitive base salary is part of our comprehensive compensation package, which includes equity and benefits. For this role, the base salary range is $206,000 - $290,000, determined by your skills, qualifications, experience and internal benchmarks.
Location:
Some roles may require being located near or on our primary sites, as indicated in the job description.
At Groq:
Our goal is to hire and promote an exceptional workforce as diverse as the global populations we serve. Groq is an equal opportunity employer committed to diversity, inclusion, and belonging in all aspects of our organization. We value and celebrate diversity in thought, beliefs, talent, expression, and backgrounds. We know that our individual differences make us better.
Groq is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans.
Groq is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: talent@groq.com. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodations will be determined on a case-by-case basis.Seniority level
Seniority levelMid-Senior level Employment type
Employment typeFull-time Job function
Job functionQuality Assurance IndustriesSemiconductor Manufacturing Referrals increase your chances of interviewing at Groq by 2x Sign in to set job alerts for “Senior Validation Engineer” roles.Computer Systems Validation, Senior ManagerSenior Quality Engineer (Design Controls and V&V) Sunnyvale, CA $126,100.00-$213,500.00 2 days ago Senior System Power Validation and Applications EngineerSenior Quality Engineer (Design Control and Risk Management) Sunnyvale, CA $126,100.00-$213,500.00 2 days ago Senior Quality Engineer (Design Control & Risk Management) Sunnyvale, CA $126,100.00-$213,500.00 2 days ago Santa Clara, CA $118,000.00-$160,000.00 2 months ago Quality Assurance Quality Control EngineerSenior Software Quality Engineer, Post MarketSenior Software Quality and Compliance Engineer - AD/ADAS SystemsSenior Software Quality Engineer (Non-Product) Alameda, CA $98,000.00-$196,000.00 1 month ago Senior Systems Engineer, Fleet Validation LeadSr Electrical Quality Engineer (Electromechanical) Alameda, CA $125,000.00-$175,000.00 1 month ago Sr Principal Engineer Quality - R10200424 Sunnyvale, CA $124,900.00-$187,300.00 2 days ago Validation Engineering Manager - SerDes, PCIe San Jose, CA $200,000.00-$270,000.00 1 week ago Manager, Systems Verification & Validation, Platform Safety Assurance Foster City, CA $189,000.00-$238,000.00 3 weeks ago Mountain View, CA $202,350.00-$303,050.00 10 hours ago Sr Principal Engineer Quality - Sunnyvale CA Sunnyvale, CA $124,900.00-$187,300.00 1 day ago Client Development Lead, Validation and Regulatory ComplianceSr. Software Engineer, HIL Automation, AutonomySenior Software Engineer, ASIC Verification ToolsSr. Software Engineer, Supply Chain Applications We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr