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Sr. Memory Controller Micro-Architect (Principal Engineer)

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role And Responsibilities

As a Sr. Memory Controller Micro-Architect, you will lead the design and development of advanced memory controllers for cutting-edge technologies such as LPDDR5, LPDDR6, PIM (Processing in Memory), and beyond (DDR5, GDDR7, HBM4). In this role, you will have ownership of the micro-architecture, RTL design, and performance/power optimization of memory controllers. You will collaborate with system architects, verification, performance/power, and design teams to develop next-generation memory technologies for Samsung, transforming innovative ideas into reality.

• Drive micro-architecture, RTL design, debugging, and timing closure for custom memory controllers, leveraging your expertise in RTL design and verification.
• Handle microarchitecture development from high-level exploration to detailed RTL implementation, ensuring performance, power, and area goals are met.
• Maintain design quality through LINT, CDC, ECO flows, and power analysis tools.
• Build strong cross-functional partnerships to ensure design functionality, achieve PPA goals, and resolve implementation challenges.
• Ensure compliance with JEDEC standards, support timing closure, and collaborate on DDR PHY integration.

Skills And Qualifications

• 20+ years of experience with a Bachelor’s in Computer Science/Engineering, or 18+ years with a Master’s, or 16+ years with a PhD.
• Proven experience in memory controller micro-architecture and RTL design, owning all sub-blocks of custom memory controllers.
• Deep expertise in memory technologies such as LPDDR4/5/6, PIM, DDR, GDDR, and HBM.
• Strong knowledge of JEDEC standards and DDR PHY.
• Experience in RTL design, verification, synthesis, and timing analysis using Verilog and ASIC flow.
• Proficiency in scripting languages like Perl and Python for automation.
• Excellent communication and collaboration skills; ability to work in a fast-paced, global environment.
• Familiarity with interface protocols (AMBA, AXI, ACE) is preferred.
• Knowledge of AES, ECC, and RAS features is a plus.

Our Team

Our System IP team develops proprietary coherent interconnect and memory controllers used in high-volume products. We focus on scalable architecture, performance, and power optimization, contributing to complex semiconductor solutions across various market segments. Join a diverse, innovative team at a global company and help shape the future of memory technology.

Total Rewards

Base pay ranges from $216,521 to $359,527, depending on experience and qualifications. Benefits include medical, dental, vision, life insurance, 401(k), onsite lunch, tuition assistance, paid time off, wellness incentives, and potential bonuses or incentives. Relocation and long-term incentives may also be available.

U.S. Export Control & Trade Secrets

This role requires access to export-controlled information, and applicants must be eligible for such access. By applying, you agree not to disclose proprietary or confidential information from previous employers.