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NVIDIA's continued advancement of world-leading hardware requires a combination of the best of both external and internal EDA tools. Our team develops and deploys these highly optimized internal tools which are used across all NVIDIA product lines many thousands of times per day. We are seeking a CAD R&D Engineer excited to innovate in algorithms related to ECO automation, including mapping, patch size minimization, reconfiguration of clocks, power, and DFT, as well as incremental timing and power optimization. A thorough understanding of both VLSI hardware design and efficient software implementations is key. Experience with GUIs would also be a big plus. ECOs involve nearly every area of the VLSI flow, so this is a particularly broad and highly visible role. Developing software within a leading hardware company means getting to almost exclusively focus on the latest processes and most advanced designs. We're not bogged down by legacy support, niche roles, or convoluted approval processes. Our developers enjoy unusually high intellectual freedom and the ability to explore broad roles. If you like to work across many technical areas and see your successes directly realized in the world's best AI hardware, this is it! What you’ll be doing: Innovate across the entire VLSI flow to make incremental recovery and optimization fast and seamless. This will primarily involve C++ and includes improving or replacing in-house algorithms for steps such as incremental CTS (clock tree synthesis), incremental scan insertion, power hookup, placement, timing optimization, etc.

Educate RTL teams on best practices that you identify and advance.

Help develop GUIs for design visualization and other tools to boost designer productivity

Over time, this role can expand to other areas of physical design implementation and analysis tools

As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

What we need to see: BS or MS in Electrical Engineering (or equivalent experience)

3+ years experience broadly across VLSI, including exposure to synthesis, clocks, DFT, power distribution, timing, and place & route. Previous experience as a physical design engineer would be ideal.

Proficiency in C++

Some familiarity with use of SAT solvers and packages for logic minimization

Insight and interest in boosting design team productivity through intuitive GUIs and APIs

Ways to stand out from the crowd: Experience with GUI frameworks, especially ImGui or Qt

Background with synthesis and timing tools, including Design Compiler, Fusion Compiler, and PrimeTime

Experience in using AI-coding assistants such as Cursor

Experience with scripting languages such as Python, Perl, or Tcl

Strong communication and interpersonal skills

NVIDIA is widely considered to be one of the technology world’s most desirable employers, and due to outstanding success, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team driving the latest in GPU and AI technology? If so, we want to hear from you! Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and

benefits . Applications for this job will be accepted at least until July 29, 2025. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr