Apple Inc.
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and hardworking Timing Design Engineer. As a member of our multifaceted group, you will have the opportunity to craft upcoming products that will delight millions of Apple’s customers every day. In this role, you will be at the center of PHY design efforts, collaborating with architecture, CAD, and logic design teams, with a critical impact on delivering outstanding PHY designs. You will be directly involved in timing closure and physical design of PHY components.
Description
As an ASIC STA Engineer, your responsibilities will include all aspects of SoC timing design. Key tasks involve timing sign-off, STA and flow development, ownership of IP and block-level timing constraints, from synthesis to sign-off, ensuring quality timing constraints. You will work closely with RTL designers to understand design intent and clock structure, with CAD to develop flows, and with the Physical Design team to achieve timing closure. You will also develop ideas and plans to verify your timing constraints, and innovate in timing constraints and flows to facilitate timing closure and address potential issues. Minimum Qualifications
BS degree in a technical discipline with at least 10 years of relevant experience. Preferred Qualifications
Thorough knowledge of ASIC design timing closure flow and methodology. At least 5+ years of experience in writing ASIC timing constraints and timing closure, expertise in STA tools (Primetime), flow, timing corners/modes, process variations, and signal integrity issues. Hands-on experience in timing/SDC constraints generation and management, proficiency in scripting languages (Tcl and Perl). Familiarity with synthesis, DFT, and backend methodologies and tools. Strong communication skills for interfacing with various groups. Self-motivated and highly driven to succeed at Apple. At Apple, base pay is part of our total compensation package and depends on skills, qualifications, experience, and location. The range for this role is between $171,600 and $302,200. Employees may also participate in stock programs, receive benefits such as medical and dental coverage, retirement plans, discounts, educational reimbursement, and may be eligible for bonuses or relocation assistance. Learn more about Apple Benefits.
Apple is an equal opportunity employer committed to diversity and inclusion, promoting equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics. Learn more about your EEO rights as an applicant. #J-18808-Ljbffr
As an ASIC STA Engineer, your responsibilities will include all aspects of SoC timing design. Key tasks involve timing sign-off, STA and flow development, ownership of IP and block-level timing constraints, from synthesis to sign-off, ensuring quality timing constraints. You will work closely with RTL designers to understand design intent and clock structure, with CAD to develop flows, and with the Physical Design team to achieve timing closure. You will also develop ideas and plans to verify your timing constraints, and innovate in timing constraints and flows to facilitate timing closure and address potential issues. Minimum Qualifications
BS degree in a technical discipline with at least 10 years of relevant experience. Preferred Qualifications
Thorough knowledge of ASIC design timing closure flow and methodology. At least 5+ years of experience in writing ASIC timing constraints and timing closure, expertise in STA tools (Primetime), flow, timing corners/modes, process variations, and signal integrity issues. Hands-on experience in timing/SDC constraints generation and management, proficiency in scripting languages (Tcl and Perl). Familiarity with synthesis, DFT, and backend methodologies and tools. Strong communication skills for interfacing with various groups. Self-motivated and highly driven to succeed at Apple. At Apple, base pay is part of our total compensation package and depends on skills, qualifications, experience, and location. The range for this role is between $171,600 and $302,200. Employees may also participate in stock programs, receive benefits such as medical and dental coverage, retirement plans, discounts, educational reimbursement, and may be eligible for bonuses or relocation assistance. Learn more about Apple Benefits.
Apple is an equal opportunity employer committed to diversity and inclusion, promoting equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics. Learn more about your EEO rights as an applicant. #J-18808-Ljbffr