Apple
Overview
Timing Design Engineer – Cupertino, California, United States
Hardware
Posted: Mar 20, 2025
Role Number: 200573372-0836
At Apple, we work every day to craft products that enrich people’s lives. This role involves working on timing design for PHY/SoC blocks, collaborating with architecture, CAD, logic design, and Physical Design teams to achieve sign‑off timing for outstanding PHY designs.
Responsibilities
As an ASIC STA Engineer, manage responsibilities spanning all aspects of SoC timing from synthesis to sign‑off to achieve timing closure.
Own IP and block level timing constraints for regular and custom timing requirements; develop timing sign‑off flows and timing closure strategies.
Collaborate with RTL designers to understand design intent and clock structure, with CAD to develop and optimize flows, and with Physical Design teams to close and sign‑off timing.
Propose ideas and plans to verify timing constraints; innovate timing constraints and flows to facilitate timing closure and mitigate potential pessimism or falls‑outs in timing analysis.
Minimum Qualifications
BS degree in technical discipline with minimum 10 years of meaningful experience.
Preferred Qualifications
Thorough knowledge of the ASIC design timing closure flow and methodology.
5+ years of experience in writing ASIC timing constraints and timing closure; expertise in STA tools (Primetime) and flow; knowledge of timing corners/modes, process variations and signal integrity issues.
Hands‑on experience in timing/SDC constraints generation and management; proficient in scripting languages (Tcl and Perl).
Familiarity with synthesis, DFT and backend related methodology and tools.
Strong communication skills and ability to interface with multiple groups.
Self‑starter and highly motivated to be successful at Apple.
Pay & Benefits The base pay range for this role is between $181,100 and $318,400, and your base pay will depend on your skills, qualifications, experience, and location. This role offers a total compensation package with the opportunity to participate in discretionary employee stock programs. Benefits include comprehensive medical and dental coverage, retirement benefits, product discounts and free services, and education reimbursement for advancing your career. Relocation and discretionary bonuses or commissions may apply. Learn more about Apple Benefits.
Notes Apple is an equal opportunity employer committed to inclusion and diversity. We promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics. Apple participates in E‑Verify where required by law. Reasonable accommodation and drug‑free workplace policies apply. Apple will consider all qualified applicants with criminal histories in a manner consistent with applicable law. For San Francisco applicants, review local fair chance guidelines.
It is unlawful in some jurisdictions to require or administer a lie detector test as a condition of employment. Other location‑specific notices may apply.
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Hardware
Posted: Mar 20, 2025
Role Number: 200573372-0836
At Apple, we work every day to craft products that enrich people’s lives. This role involves working on timing design for PHY/SoC blocks, collaborating with architecture, CAD, logic design, and Physical Design teams to achieve sign‑off timing for outstanding PHY designs.
Responsibilities
As an ASIC STA Engineer, manage responsibilities spanning all aspects of SoC timing from synthesis to sign‑off to achieve timing closure.
Own IP and block level timing constraints for regular and custom timing requirements; develop timing sign‑off flows and timing closure strategies.
Collaborate with RTL designers to understand design intent and clock structure, with CAD to develop and optimize flows, and with Physical Design teams to close and sign‑off timing.
Propose ideas and plans to verify timing constraints; innovate timing constraints and flows to facilitate timing closure and mitigate potential pessimism or falls‑outs in timing analysis.
Minimum Qualifications
BS degree in technical discipline with minimum 10 years of meaningful experience.
Preferred Qualifications
Thorough knowledge of the ASIC design timing closure flow and methodology.
5+ years of experience in writing ASIC timing constraints and timing closure; expertise in STA tools (Primetime) and flow; knowledge of timing corners/modes, process variations and signal integrity issues.
Hands‑on experience in timing/SDC constraints generation and management; proficient in scripting languages (Tcl and Perl).
Familiarity with synthesis, DFT and backend related methodology and tools.
Strong communication skills and ability to interface with multiple groups.
Self‑starter and highly motivated to be successful at Apple.
Pay & Benefits The base pay range for this role is between $181,100 and $318,400, and your base pay will depend on your skills, qualifications, experience, and location. This role offers a total compensation package with the opportunity to participate in discretionary employee stock programs. Benefits include comprehensive medical and dental coverage, retirement benefits, product discounts and free services, and education reimbursement for advancing your career. Relocation and discretionary bonuses or commissions may apply. Learn more about Apple Benefits.
Notes Apple is an equal opportunity employer committed to inclusion and diversity. We promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics. Apple participates in E‑Verify where required by law. Reasonable accommodation and drug‑free workplace policies apply. Apple will consider all qualified applicants with criminal histories in a manner consistent with applicable law. For San Francisco applicants, review local fair chance guidelines.
It is unlawful in some jurisdictions to require or administer a lie detector test as a condition of employment. Other location‑specific notices may apply.
#J-18808-Ljbffr