Digital Design Verification Engineer

Capgemini Engineering provided pay range

This range is provided by Capgemini Engineering. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$124,620.00/yr - $187,740.00/yr

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About the Job You’re Considering

We’re looking for a collaborative Digital Design Verification Engineer to help shape the future of SoC development. In this role, you’ll contribute to the validation of high-performance ARM-based systems, working across digital domains. You’ll join a supportive team that values diverse perspectives, continuous learning, and innovative problem-solving.

Your Role

• Develop and implement verification environments using SystemVerilog and UVM for IPs and SoCs with embedded CPUs.
• Create detailed test plans and coverage metrics from design specifications and execute both block- and chip-level tests.
• Collaborate with design engineers to analyze and resolve RTL and gate-level simulation issues.
• Partner with architects to simulate real-world use cases and ensure system-level functionality.

Your Skills and Experience

• Bachelor’s degree or higher in Electrical or Computer Engineering, with 5+ years of experience.
• Deep expertise in SystemVerilog, UVM, and SV Assertions, with a strong foundation in Verilog-HDL and scripting.
• Strong analytical and communication skills, with a self-driven, collaborative approach to problem-solving and automation using Python and PERL.

Seniority level

• Seniority level

  Associate

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Consulting

• Industries

  Business Consulting and Services

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Inferred from the description for this job

401(k)

Disability insurance

Medical insurance

Vision insurance

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