Design Verification Engineer at Santa Clara, CA (Onsite)

Design Verification Engineer at Santa Clara, CA (Onsite)

Design Verification Engineer at Santa Clara, CA (Onsite)

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• Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.
• Develop test plans and coverage metrics from specifications and writing block and chip-level tests.
  

• Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.
• Develop test plans and coverage metrics from specifications and writing block and chip-level tests.
  

• Synopsys/Cadence EDA Verifications tools (Preference: 5)
• SystemVerilog/UVM (Preference: 5)

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Contract

Job function

• Job function

  Engineering and Information Technology

• Industries

  Software Development

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