Tara Technical Solutions (TTS)
Packaging Engineer
Tara Technical Solutions (TTS), San Jose, California, United States, 95199
1 week ago Be among the first 25 applicants
Tara Technical Solutions (TTS) provided pay range
This range is provided by Tara Technical Solutions (TTS). Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range
$141,000.00/yr - $226,000.00/yr Direct message the job poster from Tara Technical Solutions (TTS) Tara Technical Solutions Recruiting- 24 Years of Semiconductor Recruiting.
Locations: San Jose. Austin. Fort Collins. Work on complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. Designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and contribute to efficiency improvements for our design team. RESPONSIBILITIES: Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts. Package Design of critical structures for SerDes, ADC/DAC, DDR, etc. Schedule, prioritize, & track your work across 2+ projects simultaneously Project management and customer interface for your design projects Contribute to efficiency improvements for the design team, through process development/improvement, automation, documentation, etc. Physical design (layout) is a foundational responsibility in this role EDUCATION/EXPERIENCE & REQUIREMENTS: BSEE or MSEE similar field and experience in flip-chip-BGA package design, including high-speed SerDes Knowledge of package-level signal integrity and power integrity, to apply to package designs Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK. Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers Self-management and organization skills Preferred candidates will also have 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Engineering and Design Industries Semiconductor Manufacturing, Computer Hardware Manufacturing, and Packaging and Containers Manufacturing Referrals increase your chances of interviewing at Tara Technical Solutions (TTS) by 2x Inferred from the description for this job
Medical insurance Vision insurance 401(k) Paid maternity leave Child care support Pension plan Paid paternity leave Student loan assistance Tuition assistance Disability insurance Get notified when a new job is posted. Sign in to set job alerts for “Packaging Engineer” roles.
San Francisco Bay Area $102,085.00-$132,110.00 2 weeks ago Livermore, CA $95,000.00-$135,000.00 1 week ago Santa Clara, CA $124,000.00-$171,000.00 3 days ago Sunnyvale, CA $173,000.00-$249,000.00 2 weeks ago Internship, Packaging Engineer, Supply Chain (Winter/Spring 2026)
San Jose, CA $150,938.00-$226,406.00 3 days ago Menlo Park, CA $173,000.00-$249,000.00 2 weeks ago Santa Clara, CA $165,000.00-$205,000.00 4 hours ago Sunnyvale, CA $185,000.00-$225,000.00 5 months ago Advanced Packaging Laser Engineer - Office of the CTO
Santa Clara, CA $124,000.00-$171,000.00 3 days ago Milpitas, CA $80,000.00-$115,000.00 7 hours ago Packaging Design Engineer - Advanced Wafer-Level & OSAT Processes
Santa Clara, CA $155,000.00-$275,000.00 16 hours ago Livermore, CA $105,000.00-$160,000.00 2 weeks ago Santa Clara, CA $138,000.00-$183,500.00 4 days ago Principal Advanced Packaging Technology Engineer
San Jose, CA $221,360.00-$332,040.00 5 days ago Packaging Design Engineer - Optical Interfaces
Santa Clara, CA $125,000.00-$255,000.00 16 hours ago Fremont, CA $211,000.00-$407,000.00 1 week ago Fremont, CA $110,100.00-$214,650.00 3 days ago Milpitas, CA $114,100.00-$194,000.00 2 weeks ago Milpitas, CA $95,000.00-$135,000.00 6 days ago San Jose, CA $182,756.00-$202,745.00 3 weeks ago San Jose, CA $136,500.00-$253,500.00 2 weeks ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr
This range is provided by Tara Technical Solutions (TTS). Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range
$141,000.00/yr - $226,000.00/yr Direct message the job poster from Tara Technical Solutions (TTS) Tara Technical Solutions Recruiting- 24 Years of Semiconductor Recruiting.
Locations: San Jose. Austin. Fort Collins. Work on complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. Designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and contribute to efficiency improvements for our design team. RESPONSIBILITIES: Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts. Package Design of critical structures for SerDes, ADC/DAC, DDR, etc. Schedule, prioritize, & track your work across 2+ projects simultaneously Project management and customer interface for your design projects Contribute to efficiency improvements for the design team, through process development/improvement, automation, documentation, etc. Physical design (layout) is a foundational responsibility in this role EDUCATION/EXPERIENCE & REQUIREMENTS: BSEE or MSEE similar field and experience in flip-chip-BGA package design, including high-speed SerDes Knowledge of package-level signal integrity and power integrity, to apply to package designs Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK. Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers Self-management and organization skills Preferred candidates will also have 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Job function Engineering and Design Industries Semiconductor Manufacturing, Computer Hardware Manufacturing, and Packaging and Containers Manufacturing Referrals increase your chances of interviewing at Tara Technical Solutions (TTS) by 2x Inferred from the description for this job
Medical insurance Vision insurance 401(k) Paid maternity leave Child care support Pension plan Paid paternity leave Student loan assistance Tuition assistance Disability insurance Get notified when a new job is posted. Sign in to set job alerts for “Packaging Engineer” roles.
San Francisco Bay Area $102,085.00-$132,110.00 2 weeks ago Livermore, CA $95,000.00-$135,000.00 1 week ago Santa Clara, CA $124,000.00-$171,000.00 3 days ago Sunnyvale, CA $173,000.00-$249,000.00 2 weeks ago Internship, Packaging Engineer, Supply Chain (Winter/Spring 2026)
San Jose, CA $150,938.00-$226,406.00 3 days ago Menlo Park, CA $173,000.00-$249,000.00 2 weeks ago Santa Clara, CA $165,000.00-$205,000.00 4 hours ago Sunnyvale, CA $185,000.00-$225,000.00 5 months ago Advanced Packaging Laser Engineer - Office of the CTO
Santa Clara, CA $124,000.00-$171,000.00 3 days ago Milpitas, CA $80,000.00-$115,000.00 7 hours ago Packaging Design Engineer - Advanced Wafer-Level & OSAT Processes
Santa Clara, CA $155,000.00-$275,000.00 16 hours ago Livermore, CA $105,000.00-$160,000.00 2 weeks ago Santa Clara, CA $138,000.00-$183,500.00 4 days ago Principal Advanced Packaging Technology Engineer
San Jose, CA $221,360.00-$332,040.00 5 days ago Packaging Design Engineer - Optical Interfaces
Santa Clara, CA $125,000.00-$255,000.00 16 hours ago Fremont, CA $211,000.00-$407,000.00 1 week ago Fremont, CA $110,100.00-$214,650.00 3 days ago Milpitas, CA $114,100.00-$194,000.00 2 weeks ago Milpitas, CA $95,000.00-$135,000.00 6 days ago San Jose, CA $182,756.00-$202,745.00 3 weeks ago San Jose, CA $136,500.00-$253,500.00 2 weeks ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr