SystemCanada
SCT resources have a broad range of skills in different technologies. The large skill-set has been made possible by a conscious focus on strengthening our skills base. Every person selected for our team brings something new, something that adds to our offerings. We learn continuously, both on the job and through formal training programs.
Job Description
Job Description: Physical design implementation at block or top level, low power techniques and timing closure Job Duties Include: - Will own all parts of the physical design process from netlist handoff to tapeout including floorplanning, place and route, clock tree synthesis, timing closure and physical verification - Verify effects of crosstalk, IR drop and electromigration - Very comfortable writing scripts in TCL and Perl to achieve higher performance and productivity through automation - Work very closely with logic designers, who are members of this same group, to build complex SOC's Job Requirements: - BSEE with 6+ (or MSEE with 3+) years related experience; - Physical design knowledge, from netlist handoff to GDS tapeout including floorplanning, place and route, clock tree synthesis, timing closure and physical verification - Experience with 45nm or 28nm technology - Experience with low power techniques - Experience with TCL and Perl - Excellent communication and presentation skills - Well organized, methodical and detail oriented #J-18808-Ljbffr
Job Description: Physical design implementation at block or top level, low power techniques and timing closure Job Duties Include: - Will own all parts of the physical design process from netlist handoff to tapeout including floorplanning, place and route, clock tree synthesis, timing closure and physical verification - Verify effects of crosstalk, IR drop and electromigration - Very comfortable writing scripts in TCL and Perl to achieve higher performance and productivity through automation - Work very closely with logic designers, who are members of this same group, to build complex SOC's Job Requirements: - BSEE with 6+ (or MSEE with 3+) years related experience; - Physical design knowledge, from netlist handoff to GDS tapeout including floorplanning, place and route, clock tree synthesis, timing closure and physical verification - Experience with 45nm or 28nm technology - Experience with low power techniques - Experience with TCL and Perl - Excellent communication and presentation skills - Well organized, methodical and detail oriented #J-18808-Ljbffr