OVT group
Responsibilities
Be responsible for digital design of image sensor, SoC integration and IP design, analysis, integration, and validation; work closely with back-end team in floor-planning, timing closure and DFT.
Conduct image sensor array/analog related timing control design and STA; perform chip bring-up, validation and debugging; design, integrate and validate ISP data pipes according to PRD/design specification and system architecture of SoC CIS products, following ASIC design flow: coding, simulation, synthesis, static timing analysis, formal verification, DFT, using Simvision, and EDA tools such as Prime Time, Cadence Virtuoso, Design Compiler, Integrator, and Verilog and System Verilog programming languages, etc.
Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS; work with sensor digital and analog engineers for system design, integration and validation; work with algorithm engineers for module level design, including hardware C model implementation, micro architecture design, RTL design and hardware/software co-simulation; perform software algorithm validation and cost estimation.
Work with algorithm and application engineers for image tuning and qualification; conduct silicon validation, debugging and tuning.
Qualifications
Master’s degree in Electrical Engineering, Computer Engineering, or related fields.
Knowledge and/or skills from graduate coursework include:
VLSI circuit and system design with Verilog.
Static timing analysis.
Power and area estimation.
Functional verification using ModelSim.
Digital logic circuit design.
Implementation of CPU datapath and control.
Memory hierarchy (caches, main memory, virtual memory) organization and management.
Pipelined processors.
Salary Annual base salary for this role in California, US is expected to be between $151,091 and $155,000. Actual pay will be determined by factors such as relevant skills and experience, and the pay of employees in the similar role.
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Be responsible for digital design of image sensor, SoC integration and IP design, analysis, integration, and validation; work closely with back-end team in floor-planning, timing closure and DFT.
Conduct image sensor array/analog related timing control design and STA; perform chip bring-up, validation and debugging; design, integrate and validate ISP data pipes according to PRD/design specification and system architecture of SoC CIS products, following ASIC design flow: coding, simulation, synthesis, static timing analysis, formal verification, DFT, using Simvision, and EDA tools such as Prime Time, Cadence Virtuoso, Design Compiler, Integrator, and Verilog and System Verilog programming languages, etc.
Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS; work with sensor digital and analog engineers for system design, integration and validation; work with algorithm engineers for module level design, including hardware C model implementation, micro architecture design, RTL design and hardware/software co-simulation; perform software algorithm validation and cost estimation.
Work with algorithm and application engineers for image tuning and qualification; conduct silicon validation, debugging and tuning.
Qualifications
Master’s degree in Electrical Engineering, Computer Engineering, or related fields.
Knowledge and/or skills from graduate coursework include:
VLSI circuit and system design with Verilog.
Static timing analysis.
Power and area estimation.
Functional verification using ModelSim.
Digital logic circuit design.
Implementation of CPU datapath and control.
Memory hierarchy (caches, main memory, virtual memory) organization and management.
Pipelined processors.
Salary Annual base salary for this role in California, US is expected to be between $151,091 and $155,000. Actual pay will be determined by factors such as relevant skills and experience, and the pay of employees in the similar role.
#J-18808-Ljbffr