Chelsea Search Group, Inc.
Silicon Architect Lead / Principal Engineer
Chelsea Search Group, Inc., San Jose, California, United States, 95199
Silicon Architect Lead / Principal Engineer
US Citizen or US Permanent Resident
San Jose, California or remote from any US location
Responsibilities
Establish best practices for development, testing, documentation and reviews.
Explore, define, and implement the chip/chiplet architecture for the next-gen product. Identify performance, power improvements over current micro-architecture.
Explore, identify, and integrate uncore IPs per product requirement. Define, model, and test the integration of all features for the next-gen SOC.
Help develop the system level integration for multi-chip end modules in various form factors.
Participate in strategic discussions for product features and roadmap.
Work closely with the silicon implementation, verification, and validation teams through pre/post-Si stages to ensure best-in-class PPA, microarchitecture.
Requirements
BS/MS in EE/ECE with 15+ years of VLSI industry experience in chip/SOC design
Application-specific accelerators understanding
Excellent communication and presentation skills
Hands-on experience with front end RTL, architecture, modeling, NOC/Fabric/AXI design, power management, high speed peripherals/IOs, with working experience in back-end physical design, timing convergence, DFT, DFD, EDA tools, Packaging, process and foundation libraries
Proven leadership skills and track record in multiple tapeouts, successful productizations
Self-driven with the ability to motivate and work across teams
Understanding of Systems, Advanced packaging, Ethernet, HBM, PCIe
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Responsibilities
Establish best practices for development, testing, documentation and reviews.
Explore, define, and implement the chip/chiplet architecture for the next-gen product. Identify performance, power improvements over current micro-architecture.
Explore, identify, and integrate uncore IPs per product requirement. Define, model, and test the integration of all features for the next-gen SOC.
Help develop the system level integration for multi-chip end modules in various form factors.
Participate in strategic discussions for product features and roadmap.
Work closely with the silicon implementation, verification, and validation teams through pre/post-Si stages to ensure best-in-class PPA, microarchitecture.
Requirements
BS/MS in EE/ECE with 15+ years of VLSI industry experience in chip/SOC design
Application-specific accelerators understanding
Excellent communication and presentation skills
Hands-on experience with front end RTL, architecture, modeling, NOC/Fabric/AXI design, power management, high speed peripherals/IOs, with working experience in back-end physical design, timing convergence, DFT, DFD, EDA tools, Packaging, process and foundation libraries
Proven leadership skills and track record in multiple tapeouts, successful productizations
Self-driven with the ability to motivate and work across teams
Understanding of Systems, Advanced packaging, Ethernet, HBM, PCIe
#J-18808-Ljbffr