TPI Global Solutions
Senior Recruitment Specialist at TPI Global Solutions Join a world-class team driving the development of industry-leading IP. In this role, you will be a key contributor to the verification of complex, high-speed memory controller subsystems, ensuring the delivery of the highest quality technology to the market. This is an exciting opportunity to work alongside experts in RTL design, firmware, and architecture on cutting-edge products.
Is your CV ready If so, and you are confident this is the role for you, make sure to apply asap. This is a hybrid role, requiring 2-3 days per week on-site at our client's campus in Santa Clara. Key Responsibilities
Develop and execute comprehensive verification plans for complex memory controller IP. Build, maintain, and enhance UVM-based SystemVerilog testbenches. Create directed and constrained-random tests to target specific functionality. Debug test failures, performing root cause analysis of RTL and firmware defects. Drive and analyze functional and code coverage to ensure verification completeness. Collaborate with architects and designers to understand new features and develop verification strategies. Must-Have Qualifications
10+ years of hands-on ASIC Design Verification experience. Proven expertise in
DDR or Memory Controller verification
(PHY verification is a plus). Strong proficiency with
SystemVerilog
and modern verification methodologies, especially
UVM . Excellent programming and scripting skills in languages like
C/C++ ,
Python , or
Perl . Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Details
Direct
hire approach: W2 only - No C2C Location: Santa Clara, CA (Hybrid: on-site 2-3 days per week) Employment type: Contract Job function: Design, Quality Assurance, and Information Technology Industries: Semiconductor Manufacturing, Computers and Electronics Manufacturing, and Computer Hardware Manufacturing Referrals increase your chances of interviewing at TPI Global Solutions.
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Is your CV ready If so, and you are confident this is the role for you, make sure to apply asap. This is a hybrid role, requiring 2-3 days per week on-site at our client's campus in Santa Clara. Key Responsibilities
Develop and execute comprehensive verification plans for complex memory controller IP. Build, maintain, and enhance UVM-based SystemVerilog testbenches. Create directed and constrained-random tests to target specific functionality. Debug test failures, performing root cause analysis of RTL and firmware defects. Drive and analyze functional and code coverage to ensure verification completeness. Collaborate with architects and designers to understand new features and develop verification strategies. Must-Have Qualifications
10+ years of hands-on ASIC Design Verification experience. Proven expertise in
DDR or Memory Controller verification
(PHY verification is a plus). Strong proficiency with
SystemVerilog
and modern verification methodologies, especially
UVM . Excellent programming and scripting skills in languages like
C/C++ ,
Python , or
Perl . Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Details
Direct
hire approach: W2 only - No C2C Location: Santa Clara, CA (Hybrid: on-site 2-3 days per week) Employment type: Contract Job function: Design, Quality Assurance, and Information Technology Industries: Semiconductor Manufacturing, Computers and Electronics Manufacturing, and Computer Hardware Manufacturing Referrals increase your chances of interviewing at TPI Global Solutions.
#J-18808-Ljbffr