VIVA
Overview
Title: Verification Engineer Hybrid Description: Responsibilities Create and implement a verification plan. Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design. Collaborate with the hardware design team to identify and resolve issues. Work in a UVM environment. Use of Assertions, and randomized and direct tests. Code coverage and debugging. Analyze and report on verification results.
Qualifications
BSEE or CS 10-15 years of solid experience in UVM design verification Strong knowledge of UVM verification, DV tools & methodologies Deep technical background in AISC & SOC verification Experience with CPUs & high speed I/Os Experience with Cadence or Synopsys Verification tools & Verdi Solid experience in SystemVerilog
Top 3-5 Must Have Skills
UVM SystemVerilog SoC DFx Coverage Debugging skill
Mandatory skills
UVM, UVM design verification UVM verification, UVM environment AISC, SOC AISC verification, SOC verification DV tools, DV methodologies CPU, I/O, Cadence, Synopsys Verification tools, Synopsys, Verdi System Verilog, IP, I/O SOC, UVM test bench development design verification, test plan, test verification
EEO statement:
VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions. Contact Details : Account co-ordinator: Godwin D Antony Raj VIVA USA INC. 3601 Algonquin Road, Suite 425 Rolling Meadows, IL 60008 | ;/span> . #J-18808-Ljbffr
Title: Verification Engineer Hybrid Description: Responsibilities Create and implement a verification plan. Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design. Collaborate with the hardware design team to identify and resolve issues. Work in a UVM environment. Use of Assertions, and randomized and direct tests. Code coverage and debugging. Analyze and report on verification results.
Qualifications
BSEE or CS 10-15 years of solid experience in UVM design verification Strong knowledge of UVM verification, DV tools & methodologies Deep technical background in AISC & SOC verification Experience with CPUs & high speed I/Os Experience with Cadence or Synopsys Verification tools & Verdi Solid experience in SystemVerilog
Top 3-5 Must Have Skills
UVM SystemVerilog SoC DFx Coverage Debugging skill
Mandatory skills
UVM, UVM design verification UVM verification, UVM environment AISC, SOC AISC verification, SOC verification DV tools, DV methodologies CPU, I/O, Cadence, Synopsys Verification tools, Synopsys, Verdi System Verilog, IP, I/O SOC, UVM test bench development design verification, test plan, test verification
EEO statement:
VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions. Contact Details : Account co-ordinator: Godwin D Antony Raj VIVA USA INC. 3601 Algonquin Road, Suite 425 Rolling Meadows, IL 60008 | ;/span> . #J-18808-Ljbffr