Lockheed Martin
Design Engineer ASIC & FPGA -Level 5
Lockheed Martin, Fort Worth, Texas, United States, 76102
Basic Qualifications
Bachelor's from an accredited college in Electrical or Computer Engineering or bachelor’s degree from a related discipline, or equivalent experience/combined education
Experience in the verification of FPGA and/or ASIC devices
HDL programming experience with VHDL, Verilog, and/or SystemVerilog
Secret security clearance
Job Code/Title E2525: ASIC & FPGA Design Eng Sr Stf
Job Description We are Lockheed Martin
You will be an ASIC & FPGA Design Engineer on the Microelectronics Development & Design team.
Our team makes extraordinary impact in the lives of many by developing state-of-the-art embedded systems, SoC, as well as FPGA solutions targeting F-35, F-16, and our Skunk Works IRADs.
With the team’s unique expertise in System Verilog and the Universal Verification Methodology (UVM) in verifying FPGA-based designs on Linux, we are courteously sought after for ingenious solutions to complex problems while also positively guiding, growing, and mentoring junior engineers on your team.
Beyond that, we also find ourselves doing the following:
Determining architecture design & logic of system simulation and testbenches of FPGA and ASIC designs
Creating verification test plans to achieve system functional and coverage metrics closure
Supporting internal and external technical reviews and involved in all phases of software development
Collaborating with the design team to resolve defects identified
What You Will Be Doing Your responsibilities will include:
Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development
Determines architecture design, logic design, and system simulation
Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization
Typically uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results
Must be a US citizen. This position is located at a facility that requires special access
What’s In It For You From onsite to remote, we offer flexible work schedules to comprehensive benefits investing in your future and security.
This position is in Fort Worth, TX. Fort Worth location information can be explored further for local surroundings.
Desired skills
Experience with modern verification methodologies such as UVM, OVM or VMM
Demonstrated experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test)
Knowledgeable in automated test pattern generation, logic equivalency checking, linting and/or other formal design checks
Knowledge of digital design, development, and simulation
Metrics collection, analysis, and reporting
Other Important Information By applying to this job, you are expressing interest in this position and could be considered for other career opportunities where similar skills and requirements have been identified as a match. Should this match be identified you may be contacted for this and future openings.
Security Clearance Information This position requires a government security clearance; you must be a US Citizen for consideration. Security Clearance: Secret.
EEO Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics.
Pay and Benefits National Pay Statement: The annual base salary range for this position in California and New York (excluding most major metropolitan areas), Colorado, Hawaii, Illinois, Maryland, Minnesota, New Jersey, Vermont, Washington or Washington DC is $134,000 - $236,325. For other locations, salary is based on final work location. Benefits include medical, dental, vision, life insurance, disability, 401(k) match, and more. Some regions have additional state-specific details.
Premium Pay Statement: In major metropolitan areas, base salary range is $154,100 - $267,145 with similar benefits and eligibility.
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Bachelor's from an accredited college in Electrical or Computer Engineering or bachelor’s degree from a related discipline, or equivalent experience/combined education
Experience in the verification of FPGA and/or ASIC devices
HDL programming experience with VHDL, Verilog, and/or SystemVerilog
Secret security clearance
Job Code/Title E2525: ASIC & FPGA Design Eng Sr Stf
Job Description We are Lockheed Martin
You will be an ASIC & FPGA Design Engineer on the Microelectronics Development & Design team.
Our team makes extraordinary impact in the lives of many by developing state-of-the-art embedded systems, SoC, as well as FPGA solutions targeting F-35, F-16, and our Skunk Works IRADs.
With the team’s unique expertise in System Verilog and the Universal Verification Methodology (UVM) in verifying FPGA-based designs on Linux, we are courteously sought after for ingenious solutions to complex problems while also positively guiding, growing, and mentoring junior engineers on your team.
Beyond that, we also find ourselves doing the following:
Determining architecture design & logic of system simulation and testbenches of FPGA and ASIC designs
Creating verification test plans to achieve system functional and coverage metrics closure
Supporting internal and external technical reviews and involved in all phases of software development
Collaborating with the design team to resolve defects identified
What You Will Be Doing Your responsibilities will include:
Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development
Determines architecture design, logic design, and system simulation
Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization
Typically uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results
Must be a US citizen. This position is located at a facility that requires special access
What’s In It For You From onsite to remote, we offer flexible work schedules to comprehensive benefits investing in your future and security.
This position is in Fort Worth, TX. Fort Worth location information can be explored further for local surroundings.
Desired skills
Experience with modern verification methodologies such as UVM, OVM or VMM
Demonstrated experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test)
Knowledgeable in automated test pattern generation, logic equivalency checking, linting and/or other formal design checks
Knowledge of digital design, development, and simulation
Metrics collection, analysis, and reporting
Other Important Information By applying to this job, you are expressing interest in this position and could be considered for other career opportunities where similar skills and requirements have been identified as a match. Should this match be identified you may be contacted for this and future openings.
Security Clearance Information This position requires a government security clearance; you must be a US Citizen for consideration. Security Clearance: Secret.
EEO Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics.
Pay and Benefits National Pay Statement: The annual base salary range for this position in California and New York (excluding most major metropolitan areas), Colorado, Hawaii, Illinois, Maryland, Minnesota, New Jersey, Vermont, Washington or Washington DC is $134,000 - $236,325. For other locations, salary is based on final work location. Benefits include medical, dental, vision, life insurance, disability, 401(k) match, and more. Some regions have additional state-specific details.
Premium Pay Statement: In major metropolitan areas, base salary range is $154,100 - $267,145 with similar benefits and eligibility.
#J-18808-Ljbffr