Apple Inc.
Waltham, Massachusetts, United States
Description
We work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation, low-jitter distribution, phase interpolator, DLL, VCO, LDO). We lead discussions with multi-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create and drive block-level specifications, mixed-signal implementations, and behavioral modeling. We work closely with SOC teams to deliver IP views and ensure they meet quality standards. While developing these complex IPs, we interact with peers and management to communicate progress, discuss new ideas, and drive new implementations and concepts, making it an exciting and growth-oriented environment. Minimum Qualifications
BSEE with 3+ years of proven experience. Preferred Qualifications
Deep understanding of AMS design with experience in high-speed serial links. Solid understanding of designing AMS circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, oscillators, filters. Understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power, and low-noise techniques. Experience with digitally assisted analog design concepts (e.g., background calibrations, LMS-based adaptive loops). Proven experience working on system and architecture teams to drive block-level and IP requirements. Experience with high-speed digital circuits (e.g., serializer, deserializer, counters, dividers) and digital design concepts. Experience with Tx/Rx equalization techniques for 20+ Gbps NRZ and PAM applications. Knowledge of EQ adaptation methods and circuit interactions to improve PPA. Understanding of CDR architectures and implementations. Experience in AMS circuit modeling and performance evaluation using SystemVerilog, Matlab, Python, VerilogAMS. Hands-on experience with lab testing, debugging, and data analysis. Experience with advanced CMOS technologies, including FinFET technology. Experience with AMS IC development from definition to high-volume production, including layout supervision, testing, correlation, and characterization. Additional skills in timing closure tools, IP delivery, high-speed SerDes protocols, scripting, and automation are a plus. This role offers a competitive salary range between $132,100 and $199,000, depending on skills, experience, and location. Apple provides comprehensive benefits, including medical, dental, retirement plans, stock programs, discounts, educational reimbursement, and potential bonuses or relocation assistance. Apple is an equal opportunity employer committed to diversity and inclusion. We promote equal opportunity for all applicants regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other protected characteristics.
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We work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation, low-jitter distribution, phase interpolator, DLL, VCO, LDO). We lead discussions with multi-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create and drive block-level specifications, mixed-signal implementations, and behavioral modeling. We work closely with SOC teams to deliver IP views and ensure they meet quality standards. While developing these complex IPs, we interact with peers and management to communicate progress, discuss new ideas, and drive new implementations and concepts, making it an exciting and growth-oriented environment. Minimum Qualifications
BSEE with 3+ years of proven experience. Preferred Qualifications
Deep understanding of AMS design with experience in high-speed serial links. Solid understanding of designing AMS circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, oscillators, filters. Understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power, and low-noise techniques. Experience with digitally assisted analog design concepts (e.g., background calibrations, LMS-based adaptive loops). Proven experience working on system and architecture teams to drive block-level and IP requirements. Experience with high-speed digital circuits (e.g., serializer, deserializer, counters, dividers) and digital design concepts. Experience with Tx/Rx equalization techniques for 20+ Gbps NRZ and PAM applications. Knowledge of EQ adaptation methods and circuit interactions to improve PPA. Understanding of CDR architectures and implementations. Experience in AMS circuit modeling and performance evaluation using SystemVerilog, Matlab, Python, VerilogAMS. Hands-on experience with lab testing, debugging, and data analysis. Experience with advanced CMOS technologies, including FinFET technology. Experience with AMS IC development from definition to high-volume production, including layout supervision, testing, correlation, and characterization. Additional skills in timing closure tools, IP delivery, high-speed SerDes protocols, scripting, and automation are a plus. This role offers a competitive salary range between $132,100 and $199,000, depending on skills, experience, and location. Apple provides comprehensive benefits, including medical, dental, retirement plans, stock programs, discounts, educational reimbursement, and potential bonuses or relocation assistance. Apple is an equal opportunity employer committed to diversity and inclusion. We promote equal opportunity for all applicants regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other protected characteristics.
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