Retym, Inc
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VLSI RTL Designer
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Retym, Inc We are looking for talented and experienced VLSI Design Engineers/Micro-architects. As a VLSI Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting edge communication systems from scratch. Key Responsibilities for a VLSI Design Engineer: Work closely with Algorithm and Architecture teams Understand and translate high-level algorithmic requirements into efficient hardware implementations. Learn and analyze relevant protocols and standards Interpret protocol specifications (e.g., Ethernet, etc.) and apply them accurately in design. Participate in all design stages: Micro-architecture definition RTL coding (using Verilog/SystemVerilog/VHDL) Synthesis-friendly coding and timing-aware design Collaborate cross-functionally: Verification team: For testbench development, debug support, and functional coverage closure. DFT team: Ensure design is scan-insertable, supports ATPG, BIST, etc. Backend/Physical design team: For floorplanning, timing closure, and routing feedback. Participate in Design Reviews Present and defend design decisions in peer and formal reviews. Perform Synthesis and Timing Analysis Generate synthesis constraints (SDC), run synthesis, and analyze timing reports. Debug and Fix Functional/Timing Issues Collaborate in post-silicon or pre-silicon debug; use waveforms, assertions, and logic analyzers. Optimize for Area, Power, and Performance (PPA) Identify bottlenecks and opportunities for improvement within RTL. Documentation Maintain clear design documentation for reusability and reference (e.g., micro-architecture specs, interface docs). Contribute to IP/SoC Integration Work on integrating design blocks into larger systems and handling system-level interfaces. Participate in Silicon Bring-up and Validation (optional but valuable) Support bring-up of first silicon and assist with post-silicon validation, if applicable. Keep up-to-date with Industry Trends and Tools Learn new EDA tools, languages, and methodologies (e.g., CDC, Linting, Formal Verification). Requirements: +5 years of experience as ASIC/FPGA designer Strong Verilog/System-Verilog experience Familiar with simulation tools/environments, verification methodologies Strong team player, solid interpersonal skills Entrepreneurial can-do attitude, self-motivated, able to work independently BS/MS in EE/CE from lead universities Background in one or more of the following domains is an advantage: Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT) Design DSP of oriented blocks Ethernet (100G and above) Scripting experience using several of the following: Python, Perl, TCL
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VLSI RTL Designer
role at
Retym, Inc We are looking for talented and experienced VLSI Design Engineers/Micro-architects. As a VLSI Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting edge communication systems from scratch. Key Responsibilities for a VLSI Design Engineer: Work closely with Algorithm and Architecture teams Understand and translate high-level algorithmic requirements into efficient hardware implementations. Learn and analyze relevant protocols and standards Interpret protocol specifications (e.g., Ethernet, etc.) and apply them accurately in design. Participate in all design stages: Micro-architecture definition RTL coding (using Verilog/SystemVerilog/VHDL) Synthesis-friendly coding and timing-aware design Collaborate cross-functionally: Verification team: For testbench development, debug support, and functional coverage closure. DFT team: Ensure design is scan-insertable, supports ATPG, BIST, etc. Backend/Physical design team: For floorplanning, timing closure, and routing feedback. Participate in Design Reviews Present and defend design decisions in peer and formal reviews. Perform Synthesis and Timing Analysis Generate synthesis constraints (SDC), run synthesis, and analyze timing reports. Debug and Fix Functional/Timing Issues Collaborate in post-silicon or pre-silicon debug; use waveforms, assertions, and logic analyzers. Optimize for Area, Power, and Performance (PPA) Identify bottlenecks and opportunities for improvement within RTL. Documentation Maintain clear design documentation for reusability and reference (e.g., micro-architecture specs, interface docs). Contribute to IP/SoC Integration Work on integrating design blocks into larger systems and handling system-level interfaces. Participate in Silicon Bring-up and Validation (optional but valuable) Support bring-up of first silicon and assist with post-silicon validation, if applicable. Keep up-to-date with Industry Trends and Tools Learn new EDA tools, languages, and methodologies (e.g., CDC, Linting, Formal Verification). Requirements: +5 years of experience as ASIC/FPGA designer Strong Verilog/System-Verilog experience Familiar with simulation tools/environments, verification methodologies Strong team player, solid interpersonal skills Entrepreneurial can-do attitude, self-motivated, able to work independently BS/MS in EE/CE from lead universities Background in one or more of the following domains is an advantage: Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT) Design DSP of oriented blocks Ethernet (100G and above) Scripting experience using several of the following: Python, Perl, TCL
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