Apple Inc.
Waltham, Massachusetts, United States
Description
In this role, you will be responsible for specifying and micro-architecting digital blocks in advanced mixed-signal circuits with embedded micro-controllers, advanced DFT architectures, and very low power design requirements. You will also handle RTL coding for these blocks, participate in design verification and bring-up, and work on front-end methodology flows such as pre-silicon power analysis, clock domain crossing, reset domain crossing, and unified power flow (UPF). Additionally, you will assist in lab bring-up by writing test scripts, analyzing lab data, and proposing experiments. Minimum Qualifications
BS degree in a technical discipline with at least 10 years of relevant experience. Preferred Qualifications
Deep knowledge of mixed-signal concepts Strong understanding of RTL design fundamentals (control and data path) Proficiency in Verilog and SystemVerilog Experience with front-end tools (Verilog simulators, linters, clock-domain crossing checkers, reset domain crossing, UPF) Knowledge of synthesis, static timing, and DFT (scan, analog/digital functional/production testing) Expertise in SystemVerilog assertions, checkers, and verification techniques Proficiency in scripting languages such as Perl and Python Knowledge of algorithm development Strong communication and presentation skills Knowledge of SERDES architecture is a plus At Apple, the base pay range for this role is between $162,500 and $286,400, depending on skills, qualifications, experience, and location. Employees may also participate in stock programs, receive benefits like medical and dental coverage, retirement plans, discounts, educational reimbursement, and potential bonuses or relocation assistance. Apple is an equal opportunity employer committed to diversity and inclusion. Learn more about your EEO rights as an applicant.
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In this role, you will be responsible for specifying and micro-architecting digital blocks in advanced mixed-signal circuits with embedded micro-controllers, advanced DFT architectures, and very low power design requirements. You will also handle RTL coding for these blocks, participate in design verification and bring-up, and work on front-end methodology flows such as pre-silicon power analysis, clock domain crossing, reset domain crossing, and unified power flow (UPF). Additionally, you will assist in lab bring-up by writing test scripts, analyzing lab data, and proposing experiments. Minimum Qualifications
BS degree in a technical discipline with at least 10 years of relevant experience. Preferred Qualifications
Deep knowledge of mixed-signal concepts Strong understanding of RTL design fundamentals (control and data path) Proficiency in Verilog and SystemVerilog Experience with front-end tools (Verilog simulators, linters, clock-domain crossing checkers, reset domain crossing, UPF) Knowledge of synthesis, static timing, and DFT (scan, analog/digital functional/production testing) Expertise in SystemVerilog assertions, checkers, and verification techniques Proficiency in scripting languages such as Perl and Python Knowledge of algorithm development Strong communication and presentation skills Knowledge of SERDES architecture is a plus At Apple, the base pay range for this role is between $162,500 and $286,400, depending on skills, qualifications, experience, and location. Employees may also participate in stock programs, receive benefits like medical and dental coverage, retirement plans, discounts, educational reimbursement, and potential bonuses or relocation assistance. Apple is an equal opportunity employer committed to diversity and inclusion. Learn more about your EEO rights as an applicant.
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