Intel Corporation
FVCTO - Formal Verification Architect
Intel Corporation, Santa Clara, California, United States, 95053
Job Overview
FVCTO - Formal Verification Architect at Intel Corporation.
Intel builds world‑changing technology that enriches the lives of everyone on earth. If you have a big idea, join us to create a better tomorrow.
Responsibilities
Verify microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking and equivalence checking algorithms on world class design IPs and SOCs for Server, Client and Graphics.
Use the hardware architecture design and RTL implementation details.
Define the Formal Verification scope, deploy the right strategy to prove correctness while deploying advanced formal techniques, and create abstraction models for convergence on the design.
Carve out the right boundaries for the design, create comprehensive formal verification test plans, track, verify, apply abstraction techniques, and converge on complex designs to deliver a high quality design on schedule and articulate the ROI.
Analyses new methodologies, evaluates new tools, and corroborates results.
Work with vendors to resolve hard design and tool problems.
Qualifications In addition to the qualifications, a successful candidate will demonstrate:
Problem solving and debugging skills.
Willingness to work closely with various design teams and cross site teams.
Verbal and written communication skills.
Motivated, self- directed and can work effectively both independently and in a team environment.
Minimum Qualifications
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 9 years relevant experience or schoolwork OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 6 years relevant experience or schoolwork OR PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field with 4 years relevant experience or schoolwork
Experience In The Following
RTL languages like System Verilog or VHDL. Assertion languages like SVA, formal verification.
Preferred Qualifications
The fundamentals of formal verification technology, including model checking and writing formal assertions to express architectural intent of designs.
Formal verification principles and methods.
Computer architecture, digital design and verification methods Research in formal verification domain.
Job Details Job Type: Experienced Hire
Shift: Shift 1 (United States of America)
Primary Location: US, California, Santa Clara
Additional Locations: US, California, Folsom; US, Oregon, Hillsboro; US, Texas, Austin
Business Group: Silicon Engineering Group (SIG) – a worldwide organization focused on the development and integration of SOCs, cores, and critical IPs from architecture to manufacturing readiness.
Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
Competitive pay, stock, bonuses and benefit programs which include health, retirement, and vacation.
Annual Salary Range for US locations: $186,070.00 – 303,140.00 USD.
Work Model for this Role This role will require an on‑site presence. Job posting details (such as work model, location or time type) are subject to change.
Position of Trust N/A
#J-18808-Ljbffr
Intel builds world‑changing technology that enriches the lives of everyone on earth. If you have a big idea, join us to create a better tomorrow.
Responsibilities
Verify microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking and equivalence checking algorithms on world class design IPs and SOCs for Server, Client and Graphics.
Use the hardware architecture design and RTL implementation details.
Define the Formal Verification scope, deploy the right strategy to prove correctness while deploying advanced formal techniques, and create abstraction models for convergence on the design.
Carve out the right boundaries for the design, create comprehensive formal verification test plans, track, verify, apply abstraction techniques, and converge on complex designs to deliver a high quality design on schedule and articulate the ROI.
Analyses new methodologies, evaluates new tools, and corroborates results.
Work with vendors to resolve hard design and tool problems.
Qualifications In addition to the qualifications, a successful candidate will demonstrate:
Problem solving and debugging skills.
Willingness to work closely with various design teams and cross site teams.
Verbal and written communication skills.
Motivated, self- directed and can work effectively both independently and in a team environment.
Minimum Qualifications
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 9 years relevant experience or schoolwork OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 6 years relevant experience or schoolwork OR PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field with 4 years relevant experience or schoolwork
Experience In The Following
RTL languages like System Verilog or VHDL. Assertion languages like SVA, formal verification.
Preferred Qualifications
The fundamentals of formal verification technology, including model checking and writing formal assertions to express architectural intent of designs.
Formal verification principles and methods.
Computer architecture, digital design and verification methods Research in formal verification domain.
Job Details Job Type: Experienced Hire
Shift: Shift 1 (United States of America)
Primary Location: US, California, Santa Clara
Additional Locations: US, California, Folsom; US, Oregon, Hillsboro; US, Texas, Austin
Business Group: Silicon Engineering Group (SIG) – a worldwide organization focused on the development and integration of SOCs, cores, and critical IPs from architecture to manufacturing readiness.
Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
Competitive pay, stock, bonuses and benefit programs which include health, retirement, and vacation.
Annual Salary Range for US locations: $186,070.00 – 303,140.00 USD.
Work Model for this Role This role will require an on‑site presence. Job posting details (such as work model, location or time type) are subject to change.
Position of Trust N/A
#J-18808-Ljbffr