Intel Corporation
FVCTO - Formal Verification Architect
Intel Corporation, Hillsboro, Oregon, United States, 97104
Overview
Join to apply for the
FVCTO - Formal Verification Architect
role at
Intel Corporation . Position details, location, and other role-specific information are listed below. Responsibilities
Verify microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking and equivalence checking algorithms on world class design IPs and SOCs for Server, Client and Graphics. Use the hardware architecture design and RTL implementation details. Define the Formal Verification scope, deploy the right strategy to prove correctness while deploying advanced formal techniques, and create abstraction models for convergence on the design. Carve out the right boundaries for the design, create comprehensive formal verification test plans, track, verify, apply abstraction techniques, and converge on complex designs to deliver a high-quality design on schedule and articulate the ROI. Analyze new methodologies, evaluate new tools, and corroborate results. Work with vendors to resolve hard design and tool problems. Qualifications
Minimum Qualifications The candidate must possess the following: Bachelor\'s Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 9 years relevant experience or schoolwork OR Master\'s Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 6 years relevant experience or schoolwork OR PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field with 4 years relevant experience or schoolwork. Experience In The Following RTL languages like System Verilog or VHDL; Assertion languages like SVA; formal verification. Preferred Qualifications Experience with the fundamentals of formal verification technology, including model checking and writing formal assertions to express architectural intent of designs; formal verification principles and methods; computer architecture, digital design and verification methods; research in formal verification domain. Job Details
Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, California (Folsom), US, Oregon (Hillsboro), US, Texas (Austin) Business Group: The Silicon Engineering Group (SIG) Work Model
This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change. Benefits and Compensation
We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock, bonuses, and benefit programs (health, retirement, vacation). Annual salary range for jobs which could be performed in the US:
$186,070.00-303,140.00 USD . The range reflects minimum and maximum target compensation across US locations; specific compensation is location-dependent. More information about benefits is available via the company intranet/HR pages. Required Location Information
Primary location: US, California, Santa Clara. Other listed locations include Beaverton, Beaverton/Northwest area, Portland, Hillsboro, and Beaverton, OR. Individual postings may vary by location. Additional
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, ancestry, age, disability, medical condition, genetic information, military/veteran status, marital status, pregnancy, gender identity or expression, sexual orientation, or any other characteristic protected by law.
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Join to apply for the
FVCTO - Formal Verification Architect
role at
Intel Corporation . Position details, location, and other role-specific information are listed below. Responsibilities
Verify microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking and equivalence checking algorithms on world class design IPs and SOCs for Server, Client and Graphics. Use the hardware architecture design and RTL implementation details. Define the Formal Verification scope, deploy the right strategy to prove correctness while deploying advanced formal techniques, and create abstraction models for convergence on the design. Carve out the right boundaries for the design, create comprehensive formal verification test plans, track, verify, apply abstraction techniques, and converge on complex designs to deliver a high-quality design on schedule and articulate the ROI. Analyze new methodologies, evaluate new tools, and corroborate results. Work with vendors to resolve hard design and tool problems. Qualifications
Minimum Qualifications The candidate must possess the following: Bachelor\'s Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 9 years relevant experience or schoolwork OR Master\'s Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 6 years relevant experience or schoolwork OR PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field with 4 years relevant experience or schoolwork. Experience In The Following RTL languages like System Verilog or VHDL; Assertion languages like SVA; formal verification. Preferred Qualifications Experience with the fundamentals of formal verification technology, including model checking and writing formal assertions to express architectural intent of designs; formal verification principles and methods; computer architecture, digital design and verification methods; research in formal verification domain. Job Details
Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, California (Folsom), US, Oregon (Hillsboro), US, Texas (Austin) Business Group: The Silicon Engineering Group (SIG) Work Model
This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change. Benefits and Compensation
We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock, bonuses, and benefit programs (health, retirement, vacation). Annual salary range for jobs which could be performed in the US:
$186,070.00-303,140.00 USD . The range reflects minimum and maximum target compensation across US locations; specific compensation is location-dependent. More information about benefits is available via the company intranet/HR pages. Required Location Information
Primary location: US, California, Santa Clara. Other listed locations include Beaverton, Beaverton/Northwest area, Portland, Hillsboro, and Beaverton, OR. Individual postings may vary by location. Additional
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, ancestry, age, disability, medical condition, genetic information, military/veteran status, marital status, pregnancy, gender identity or expression, sexual orientation, or any other characteristic protected by law.
#J-18808-Ljbffr