Qualcomm
Principal Design Verification Engineer - QGOV
Qualcomm, San Diego, California, United States, 92189
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Company: Qualcomm Technologies, Inc.
Job Area: Engineering Group > ASICS Engineering
General Summary Design Verification
Role
Familiarity with RTL design in Verilog and System Verilog
Develop verification methodology, ensuring scalable and portable environment across simulation and emulation.
Develop test plan to verify Hardware building blocks, Design macros and Standard interfaces (PCIE, DDR, USB, I2C, SPI, etc).
Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals.
Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches.
Develop and maintain emulation environment to collect metrics related to emulation environment.
Must be in San Diego full time, 5 days a week.
Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.
Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.
Required Qualifications
10+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture.
10+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flows.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
Pay Range And Other Compensation & Benefits $192,000.00 - $288,000.00
EEO Employer Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Employment type Full-time
Seniority level Not Applicable
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Get AI-powered advice on this job and more exclusive features.
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Continue with Google
Company: Qualcomm Technologies, Inc.
Job Area: Engineering Group > ASICS Engineering
General Summary Design Verification
Role
Familiarity with RTL design in Verilog and System Verilog
Develop verification methodology, ensuring scalable and portable environment across simulation and emulation.
Develop test plan to verify Hardware building blocks, Design macros and Standard interfaces (PCIE, DDR, USB, I2C, SPI, etc).
Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals.
Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches.
Develop and maintain emulation environment to collect metrics related to emulation environment.
Must be in San Diego full time, 5 days a week.
Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.
Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.
Required Qualifications
10+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture.
10+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flows.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
Pay Range And Other Compensation & Benefits $192,000.00 - $288,000.00
EEO Employer Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Employment type Full-time
Seniority level Not Applicable
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