Mindlance
Overview
We are seeking a talented and driven Silicon Digital Design Engineer to join our team. In this role, you will be responsible for the architecture, design, integration, and verification of advanced ASIC and SoC solutions. You will collaborate with cross-functional teams to deliver high-performance silicon products from concept to production. Responsibilities
Develop efficient digital microarchitectures and contribute to ASIC digital architecture, design, and verification. Integrate IPs and drive top-level microarchitecture definition and RTL development. Lead chip-level integration, verification plan development, and execution. Supervise the RTL-to-GDS flow, including synthesis and timing closure. Support test program development, chip validation, and product maturity. Collaborate with FPGA engineers for early prototyping and validation. Assist with algorithm analysis, verification, and improvement. Support hand-off and integration of blocks into larger SoC environments. Apply Design for Verification concepts throughout the design process. Must-Have Qualifications
4+ years of experience as a Digital Design Engineer and/or Chip Lead. Strong experience in RTL coding, synthesis, and/or SoC integration. Solid background in digital design microarchitecture. Proficiency with Verilog and SystemVerilog coding. Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience. Experience with UPF-based simulation flow. SystemVerilog OVM/UVM experience. Scripting experience with Tcl and Python (or similar). Experience in SoC integration and ASIC architecture. Nice-to-Have Qualifications
Experience with DFT/Testability requirements and test program definition. Familiarity with high-speed interfaces (PCIe, USB, MIPI). FPGA design experience. Knowledge of Tensilica DSP, TIE, CNN, fixed point, floating point, and Python. Experience with Power Aware GLS flow. Master’s degree in Electrical/Computer Engineering or Computer Science. Equal Opportunity and Fair Chance
Pursuant to the California Fair Chance Act, Los Angeles County Fair Chance Ordinance for Employers, Los Angeles Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair Chance Ordinance, qualified applicants will be considered for assignment with arrest and conviction records. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, meet client expectations, standards, and accompanying requirements, and safeguard business operations and company reputation. EEO: “Mindlance is an Equal Opportunity Employer and does not discriminate in employment on the basis of – Minority/Gender/Disability/Religion/LGBTQI/Age/Veterans.”
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We are seeking a talented and driven Silicon Digital Design Engineer to join our team. In this role, you will be responsible for the architecture, design, integration, and verification of advanced ASIC and SoC solutions. You will collaborate with cross-functional teams to deliver high-performance silicon products from concept to production. Responsibilities
Develop efficient digital microarchitectures and contribute to ASIC digital architecture, design, and verification. Integrate IPs and drive top-level microarchitecture definition and RTL development. Lead chip-level integration, verification plan development, and execution. Supervise the RTL-to-GDS flow, including synthesis and timing closure. Support test program development, chip validation, and product maturity. Collaborate with FPGA engineers for early prototyping and validation. Assist with algorithm analysis, verification, and improvement. Support hand-off and integration of blocks into larger SoC environments. Apply Design for Verification concepts throughout the design process. Must-Have Qualifications
4+ years of experience as a Digital Design Engineer and/or Chip Lead. Strong experience in RTL coding, synthesis, and/or SoC integration. Solid background in digital design microarchitecture. Proficiency with Verilog and SystemVerilog coding. Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience. Experience with UPF-based simulation flow. SystemVerilog OVM/UVM experience. Scripting experience with Tcl and Python (or similar). Experience in SoC integration and ASIC architecture. Nice-to-Have Qualifications
Experience with DFT/Testability requirements and test program definition. Familiarity with high-speed interfaces (PCIe, USB, MIPI). FPGA design experience. Knowledge of Tensilica DSP, TIE, CNN, fixed point, floating point, and Python. Experience with Power Aware GLS flow. Master’s degree in Electrical/Computer Engineering or Computer Science. Equal Opportunity and Fair Chance
Pursuant to the California Fair Chance Act, Los Angeles County Fair Chance Ordinance for Employers, Los Angeles Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair Chance Ordinance, qualified applicants will be considered for assignment with arrest and conviction records. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, meet client expectations, standards, and accompanying requirements, and safeguard business operations and company reputation. EEO: “Mindlance is an Equal Opportunity Employer and does not discriminate in employment on the basis of – Minority/Gender/Disability/Religion/LGBTQI/Age/Veterans.”
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