TPI Global Solutions
AMD is seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of AMD-Xilinx FPGA Architecture. In this role, you will design Register-Transfer Level (RTL) Intellectual Property (IP) with a focus on video connectivity subsystems. You will have dynamic, multi-faceted responsibilities in areas such as project definition, RTL design, and implementation. You will participate in the design, architecture, documentation, and implementation of the low latency video connectivity systems. You will also be responsible for RTL coding of blocks specified by you or others. Additionally, you will be responsible for various front-end methodology flows that include resource optimization, clock domain crossing and reset domain crossing.
Overview Hybrid Role in San Jose, CA. Interview process is with MS Teams.
Responsibilities
Design RTL IP (Verilog/SystemVerilog) with a focus on video connectivity subsystems.
Contribute to project definition, architecture, documentation, and implementation of low latency video connectivity systems.
RTL coding for blocks defined by you or others and contribute to front-end methodology flows (resource optimization, clock domain crossing, reset domain crossing).
Collaborate with cross-functional teams across time zones to drive design and integration.
Qualifications
Direct experience with RTL IP design using Verilog/SystemVerilog.
Proven experience working on video domain IPs or digital IPs.
Proven experience with one or more IP-level protocols: MIPI CSI, MIPI DSI, DisplayPort, HDMI, SDI.
Hands-on experience with AMD/Xilinx FPGA devices and the Vivado toolchain.
Hands-on experience with architecting, micro-architecture, and detailed design from functional specifications.
Hands-on experience with synthesizable Verilog/SystemVerilog RTL coding for FPGA designs.
Experience with lint, CDC, synthesis flows, static timing analysis, formal checking, etc.
Working knowledge of TCL, Perl, Python (added advantage).
Knowledge of SERDES architecture is a plus.
Strong desire to learn and explore new technologies.
Strong communication and presentation skills.
Note: The original description included multiple role-related headings and city/salary blocks not essential to the core responsibilities. This refined version retains the essential job content and removes extraneous boilerplate.
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Overview Hybrid Role in San Jose, CA. Interview process is with MS Teams.
Responsibilities
Design RTL IP (Verilog/SystemVerilog) with a focus on video connectivity subsystems.
Contribute to project definition, architecture, documentation, and implementation of low latency video connectivity systems.
RTL coding for blocks defined by you or others and contribute to front-end methodology flows (resource optimization, clock domain crossing, reset domain crossing).
Collaborate with cross-functional teams across time zones to drive design and integration.
Qualifications
Direct experience with RTL IP design using Verilog/SystemVerilog.
Proven experience working on video domain IPs or digital IPs.
Proven experience with one or more IP-level protocols: MIPI CSI, MIPI DSI, DisplayPort, HDMI, SDI.
Hands-on experience with AMD/Xilinx FPGA devices and the Vivado toolchain.
Hands-on experience with architecting, micro-architecture, and detailed design from functional specifications.
Hands-on experience with synthesizable Verilog/SystemVerilog RTL coding for FPGA designs.
Experience with lint, CDC, synthesis flows, static timing analysis, formal checking, etc.
Working knowledge of TCL, Perl, Python (added advantage).
Knowledge of SERDES architecture is a plus.
Strong desire to learn and explore new technologies.
Strong communication and presentation skills.
Note: The original description included multiple role-related headings and city/salary blocks not essential to the core responsibilities. This refined version retains the essential job content and removes extraneous boilerplate.
#J-18808-Ljbffr