Majestic Labs ai
SoC Architect
We are looking for a seasoned SoC Architect to lead the design and integration of the management subsystem within Majestic’s AI acceleration platform.
In this role, you will define and drive SoC-level architecture for control and management flows—integrating ARM cores, interconnects, high-speed IO, and system management interfaces. You’ll collaborate closely with peer architects, hardware, firmware, and system engineers to ensure a cohesive, high-performance design that bridges silicon and software seamlessly.
This is a hands‑on architecture role that combines technical depth, system‑level thinking, and cross‑domain leadership in a fast‑moving startup environment.
What You’ll Do
Define and own the
management subsystem architecture
for Majestic’s AI SoC.
Integrate
ARM cores
(CSS / Cortex‑A) and associated subsystems for control, configuration, and monitoring.
Architect
PCIe connectivity
and high‑bandwidth IO to ensure robust host and device communication.
Specify and integrate
DDR/LPDDR interfaces
and memory management structures.
Design peripheral and control interfaces, including
SPI, I2C, UART, GPIO , and system control buses.
Develop
scheduler and interrupt schemes , driver‑facing control paths, and configuration frameworks.
Integrate and optimize
debug and trace infrastructures
(CoreSight, profilers, diagnostic tools).
Collaborate with RTL, verification, firmware, and board teams to ensure seamless hardware‑software co‑design.
Drive trade‑offs and decisions to achieve performance, power, and area targets across the SoC.
Requirements
Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field.
6+ years of experience in
SoC architecture and design , with emphasis on
management or control subsystems .
Proven experience with
ARM core integration ,
PCIe ,
DDR/LPDDR , and
peripheral interfaces (SPI, I2C, UART) .
Strong understanding of
SoC design flows , memory hierarchy, and interconnect fabrics.
Hands‑on experience in
control path design ,
driver interfaces , and
interrupt management .
Solid communication and teamwork skills, with the ability to lead cross‑functional architectural discussions.
Ways to Stand Out
Experience with
AI/ML acceleration hardware
or
high‑performance compute SoCs .
Knowledge of
board‑level integration
and
hardware‑software co‑validation .
Familiarity with
silicon prototyping, emulation, or FPGA‑based validation .
Expertise in
low‑power design
and
high‑bandwidth interconnect architectures .
Deep experience with
debug tools
(CoreSight, trace analyzers, profilers) and performance instrumentation.
#J-18808-Ljbffr
In this role, you will define and drive SoC-level architecture for control and management flows—integrating ARM cores, interconnects, high-speed IO, and system management interfaces. You’ll collaborate closely with peer architects, hardware, firmware, and system engineers to ensure a cohesive, high-performance design that bridges silicon and software seamlessly.
This is a hands‑on architecture role that combines technical depth, system‑level thinking, and cross‑domain leadership in a fast‑moving startup environment.
What You’ll Do
Define and own the
management subsystem architecture
for Majestic’s AI SoC.
Integrate
ARM cores
(CSS / Cortex‑A) and associated subsystems for control, configuration, and monitoring.
Architect
PCIe connectivity
and high‑bandwidth IO to ensure robust host and device communication.
Specify and integrate
DDR/LPDDR interfaces
and memory management structures.
Design peripheral and control interfaces, including
SPI, I2C, UART, GPIO , and system control buses.
Develop
scheduler and interrupt schemes , driver‑facing control paths, and configuration frameworks.
Integrate and optimize
debug and trace infrastructures
(CoreSight, profilers, diagnostic tools).
Collaborate with RTL, verification, firmware, and board teams to ensure seamless hardware‑software co‑design.
Drive trade‑offs and decisions to achieve performance, power, and area targets across the SoC.
Requirements
Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field.
6+ years of experience in
SoC architecture and design , with emphasis on
management or control subsystems .
Proven experience with
ARM core integration ,
PCIe ,
DDR/LPDDR , and
peripheral interfaces (SPI, I2C, UART) .
Strong understanding of
SoC design flows , memory hierarchy, and interconnect fabrics.
Hands‑on experience in
control path design ,
driver interfaces , and
interrupt management .
Solid communication and teamwork skills, with the ability to lead cross‑functional architectural discussions.
Ways to Stand Out
Experience with
AI/ML acceleration hardware
or
high‑performance compute SoCs .
Knowledge of
board‑level integration
and
hardware‑software co‑validation .
Familiarity with
silicon prototyping, emulation, or FPGA‑based validation .
Expertise in
low‑power design
and
high‑bandwidth interconnect architectures .
Deep experience with
debug tools
(CoreSight, trace analyzers, profilers) and performance instrumentation.
#J-18808-Ljbffr