Etched
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This range is provided by Etched. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base Pay Range $220,000.00/yr - $280,000.00/yr
Additional Compensation Types Annual Bonus and Stock options
Substrate IC Package Layout Design Engineer Role Summary: As a
Substrate IC Package Layout Design Engineer , you will be responsible for the end-to-end design of complex IC substrate packages, supporting high-power consumption and high-speed signaling. The ideal candidate will have extensive experience with large substrate designs (>50mm), complex power delivery networks, and high-speed signaling solutions (up to and beyond 50GHz). You will work closely with silicon, signal integrity, power integrity, and system help co‑design world class substates with OSAT providers. Intense focus on optimization for power delivery through substrate, pushing what’s possible.
Key Responsibilities
IC Substrate Layout Design
Lead the design and development of complex IC substrate layouts for high‑power AI processors and accelerators.
Design large (>50mm) and complex multi‑layer substrate packages with high pin counts and dense routing requirements.
Ensure robust power delivery designs capable of supporting >700W custom silicon solutions.
High‑Speed Signal Routing & Integrity
Develop high‑speed signal routing solutions capable of supporting >50GHz signaling while minimizing signal integrity issues such as loss and crosstalk.
Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and implement solutions in substrate layout.
Advanced Packaging & CoWoS Integration
Optimize CoWoS (Chip‑on‑Wafer‑on‑Substrate) interposer designs for thermal and electrical performance.
Work closely with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability.
Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs.
Develop and maintain design documentation and guidelines for future substrate designs.
Support design reviews and provide technical guidance to junior team members.
You May Be a Good Fit If You Have
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience
in IC substrate layout design for high‑performance processors or accelerators.
Extensive experience with large substrate packages (>50mm) and complex high‑density layouts.
Proven experience with
high‑power (700W+) package designs
and robust power delivery networks.
Expertise in high‑speed signaling design (>50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches).
Strong experience with
CoWoS (Chip‑on‑Wafer‑on‑Substrate) interposer design
and the impact of the substrate design to support CoWos.
Advanced proficiency in
Allegro Package Designer
(including constraint management, routing, and design verification).
Deep understanding of SI/PI principles and how they apply to package‑level design.
Strong analytical skills and ability to work effectively in a fast‑paced, cross‑functional team environment.
Full medical, dental, and vision packages, with generous premium coverage.
Housing subsidy of
$2,000/month
for those living within walking distance of the office.
Daily lunch and dinner in our office.
Relocation support for those moving to West San Jose.
Compensation Range
$220,000 - $275,000 + Bonus + Equity
How We’re Different Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model‑specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single‑model ASICs.
We are a fully in‑person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Seniority Level Mid‑Senior level
Employment Type Full‑time
Job Function Design, Art/Creative, and Information Technology
Industries: Computer Hardware Manufacturing
Referrals increase your chances of interviewing at Etched by 2x
Get notified about new Package Engineer jobs in
San Jose, CA .
#J-18808-Ljbffr
This range is provided by Etched. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base Pay Range $220,000.00/yr - $280,000.00/yr
Additional Compensation Types Annual Bonus and Stock options
Substrate IC Package Layout Design Engineer Role Summary: As a
Substrate IC Package Layout Design Engineer , you will be responsible for the end-to-end design of complex IC substrate packages, supporting high-power consumption and high-speed signaling. The ideal candidate will have extensive experience with large substrate designs (>50mm), complex power delivery networks, and high-speed signaling solutions (up to and beyond 50GHz). You will work closely with silicon, signal integrity, power integrity, and system help co‑design world class substates with OSAT providers. Intense focus on optimization for power delivery through substrate, pushing what’s possible.
Key Responsibilities
IC Substrate Layout Design
Lead the design and development of complex IC substrate layouts for high‑power AI processors and accelerators.
Design large (>50mm) and complex multi‑layer substrate packages with high pin counts and dense routing requirements.
Ensure robust power delivery designs capable of supporting >700W custom silicon solutions.
High‑Speed Signal Routing & Integrity
Develop high‑speed signal routing solutions capable of supporting >50GHz signaling while minimizing signal integrity issues such as loss and crosstalk.
Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and implement solutions in substrate layout.
Advanced Packaging & CoWoS Integration
Optimize CoWoS (Chip‑on‑Wafer‑on‑Substrate) interposer designs for thermal and electrical performance.
Work closely with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability.
Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs.
Develop and maintain design documentation and guidelines for future substrate designs.
Support design reviews and provide technical guidance to junior team members.
You May Be a Good Fit If You Have
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience
in IC substrate layout design for high‑performance processors or accelerators.
Extensive experience with large substrate packages (>50mm) and complex high‑density layouts.
Proven experience with
high‑power (700W+) package designs
and robust power delivery networks.
Expertise in high‑speed signaling design (>50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches).
Strong experience with
CoWoS (Chip‑on‑Wafer‑on‑Substrate) interposer design
and the impact of the substrate design to support CoWos.
Advanced proficiency in
Allegro Package Designer
(including constraint management, routing, and design verification).
Deep understanding of SI/PI principles and how they apply to package‑level design.
Strong analytical skills and ability to work effectively in a fast‑paced, cross‑functional team environment.
Full medical, dental, and vision packages, with generous premium coverage.
Housing subsidy of
$2,000/month
for those living within walking distance of the office.
Daily lunch and dinner in our office.
Relocation support for those moving to West San Jose.
Compensation Range
$220,000 - $275,000 + Bonus + Equity
How We’re Different Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model‑specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single‑model ASICs.
We are a fully in‑person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Seniority Level Mid‑Senior level
Employment Type Full‑time
Job Function Design, Art/Creative, and Information Technology
Industries: Computer Hardware Manufacturing
Referrals increase your chances of interviewing at Etched by 2x
Get notified about new Package Engineer jobs in
San Jose, CA .
#J-18808-Ljbffr