Microsoft
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is behind Microsoft’s expanding Cloud Infrastructure and supports the Intelligent Cloud mission. This role is part of the Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team.
Responsibilities
Design and drive high-performance, high-bandwidth Compute and Network-on-Chip architectures for cutting‑edge AI SoCs.
Specify microarchitecture, author RTL in Verilog/System Verilog, and manage CDC, lint, synthesis, and FEV activities.
Integrate IP into System-on-Chip subsystems and collaborate with architecture, verification, and physical teams to ensure specification compliance.
Qualifications
Required/Minimum Qualifications:
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
OR Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
OR Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
OR equivalent experience.
5+ years expertise in Digital Design, including microarchitecture specification, RTL coding, and CDC/lint closure.
5+ years of experience delivering successful IP or Application Specific Integrated Circuit (ASIC)/System-on-Chip (SOC) designs.
4+ years of experience in synthesis, timing constraints, power, performance, area (PPA) tradeoffs, and post‑silicon debug.
4+ years of experience designing Fabric/Network‑on‑Chip or Networking ASICs or complex control logic.
Other Requirements Ability to meet Microsoft, customer and/or government security screening requirements is required. This includes a Microsoft Cloud Background Check upon hire and biennially thereafter, as well as export‑control clearance for access to controlled information.
Additional or Preferred Qualifications
CPU or graphics core design.
Complex algorithmic designs for AI usages.
Script development skills.
Silicon Engineering IC4 – Base pay range: USD $119,800 – $234,700 per year (US). Location adjustments: $158,400 – $258,000 in San Francisco Bay Area and NYC metro. Additional benefits and compensation may apply.
Applications accepted until Nov 6, 2025.
Microsoft is an equal‑opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex, sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances.
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Responsibilities
Design and drive high-performance, high-bandwidth Compute and Network-on-Chip architectures for cutting‑edge AI SoCs.
Specify microarchitecture, author RTL in Verilog/System Verilog, and manage CDC, lint, synthesis, and FEV activities.
Integrate IP into System-on-Chip subsystems and collaborate with architecture, verification, and physical teams to ensure specification compliance.
Qualifications
Required/Minimum Qualifications:
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
OR Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
OR Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
OR equivalent experience.
5+ years expertise in Digital Design, including microarchitecture specification, RTL coding, and CDC/lint closure.
5+ years of experience delivering successful IP or Application Specific Integrated Circuit (ASIC)/System-on-Chip (SOC) designs.
4+ years of experience in synthesis, timing constraints, power, performance, area (PPA) tradeoffs, and post‑silicon debug.
4+ years of experience designing Fabric/Network‑on‑Chip or Networking ASICs or complex control logic.
Other Requirements Ability to meet Microsoft, customer and/or government security screening requirements is required. This includes a Microsoft Cloud Background Check upon hire and biennially thereafter, as well as export‑control clearance for access to controlled information.
Additional or Preferred Qualifications
CPU or graphics core design.
Complex algorithmic designs for AI usages.
Script development skills.
Silicon Engineering IC4 – Base pay range: USD $119,800 – $234,700 per year (US). Location adjustments: $158,400 – $258,000 in San Francisco Bay Area and NYC metro. Additional benefits and compensation may apply.
Applications accepted until Nov 6, 2025.
Microsoft is an equal‑opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex, sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances.
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