Russell Tobin
This range is provided by Russell Tobin. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range
$70.00/hr - $74.00/hr
Contract type:
12 months W2 with possible extensions
Pay Rate:
$70-74/hour
About the Role Join a world-class SoC development team delivering industry-leading mixed‑signal IP in advanced CMOS and FinFET process nodes. You will partner closely with circuit design engineers to produce high‑performance, fully verified layouts powering next‑generation products.
Key Responsibilities
Layout development for mixed‑signal and analog circuits in deep sub‑micron CMOS and FinFET technologies
Analyze and optimize floorplans, parasitics, and physical constraints
Execute full physical verification flows (DRC, LVS, ERC) and resolve violations
Coordinate directly with design teams on schedules, ECOs, and layout trade‑offs
Optimize for performance, area, and power across layout deliverables
Apply advanced CAD tools and methodologies to drive automation and consistency
Contribute to layout best practices and continuous improvement initiatives
Required Qualifications
5+ years analog/mixed‑signal layout experience
2+ years FinFET technology experience
Strong expertise in deep sub‑micron CMOS environments
Proficiency with Virtuoso, Innovus, Calibre, or similar EDA tools
Solid understanding of verification workflows and physical design rules
Strong communication and cross‑functional collaboration skills
Preferred
SKILL, Perl, and/or Python scripting
Experience or academic focus in RF / Mixed‑Signal ICs
Seniority level Associate
Employment type Contract
Job function Engineering, Information Technology, and Manufacturing
Industries Semiconductor Manufacturing, Retail Appliances, Electrical, and Electronic Equipment, and Computers and Electronics Manufacturing
Benefits
Medical insurance
Vision insurance
401(k)
#J-18808-Ljbffr
Base pay range
$70.00/hr - $74.00/hr
Contract type:
12 months W2 with possible extensions
Pay Rate:
$70-74/hour
About the Role Join a world-class SoC development team delivering industry-leading mixed‑signal IP in advanced CMOS and FinFET process nodes. You will partner closely with circuit design engineers to produce high‑performance, fully verified layouts powering next‑generation products.
Key Responsibilities
Layout development for mixed‑signal and analog circuits in deep sub‑micron CMOS and FinFET technologies
Analyze and optimize floorplans, parasitics, and physical constraints
Execute full physical verification flows (DRC, LVS, ERC) and resolve violations
Coordinate directly with design teams on schedules, ECOs, and layout trade‑offs
Optimize for performance, area, and power across layout deliverables
Apply advanced CAD tools and methodologies to drive automation and consistency
Contribute to layout best practices and continuous improvement initiatives
Required Qualifications
5+ years analog/mixed‑signal layout experience
2+ years FinFET technology experience
Strong expertise in deep sub‑micron CMOS environments
Proficiency with Virtuoso, Innovus, Calibre, or similar EDA tools
Solid understanding of verification workflows and physical design rules
Strong communication and cross‑functional collaboration skills
Preferred
SKILL, Perl, and/or Python scripting
Experience or academic focus in RF / Mixed‑Signal ICs
Seniority level Associate
Employment type Contract
Job function Engineering, Information Technology, and Manufacturing
Industries Semiconductor Manufacturing, Retail Appliances, Electrical, and Electronic Equipment, and Computers and Electronics Manufacturing
Benefits
Medical insurance
Vision insurance
401(k)
#J-18808-Ljbffr