Hubble Network
About Hubble
Hubble Network was founded with the intention of delivering on the promise of what Internet-of-Things (IoT) was supposed to be. We're building a global Bluetooth® network dedicated to machine-to-machine connectivity. We differentiate ourselves as the first modem-less and gateway-less, direct-to-satellite network from off-the-shelf Bluetooth® Low Energy chips. Hubble is ideal for applications in logistics, AgTech, and maritime where economies of scale for volume consumer and enterprise asset tracking is a priority. Our goal is to be the first billion-endpoint-connected network in the world.
Hubble is an early-stage, venture-backed startup supported by some of the best investors in the world. In their previous lives, the founding team has been successful in raising $100s of millions in venture funding, developing the Amazon Sidewalk network, launching billions of dollars of space assets, and leading their teams to successful exits, both through acquisition and IPO. We are now looking to bring on talented team members who are the best at what they do to help us make Hubble a reality for the world.
Position Overview As a
Digital Design Engineer , you will play a key role in developing the RTL codebase for the FPGA module that performs localization and decodes packets from ground-based BLE device transmissions. You’ll collaborate closely with a cross‑functional team of system, hardware, and software engineers to optimize the throughput, accuracy, power efficiency, and reliability of the Hubble satellite constellation.
This is a full-time position based in Seattle, WA.
AN IDEAL CANDIDATE HAS
Sense of Urgency:
Lead projects from concept to reality, rapidly and effectively
First Principles Engineering:
Have a strong understanding of the whys behind the whats; have the ability to extrapolate from first principles to complex system design
High Learning Agility:
Love to learn; have a grounded approach to recognizing your weaknesses and take the initiative to brush up on and sharpen your engineering foundations to better collaborate with your teammates with different backgrounds
System‑Level Design and Analysis:
Understand the requirements flow down process and be able to quickly iterate on evolving requirements
Excellent Communication Skills:
Effectively convey ideas and communicate technical topics with engineering, build staff, and operations; run self‑directed design reviews and participate in reviews of parallel systems
Anticipation of Needs:
Identify problems, think creatively, and rapidly produce reliable and cost‑effective solutions to meet the ever growing and changing needs of an early‑stage company
BASIC QUALIFICATIONS
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
2-5 years of experience
in FPGA‑based digital design, with a strong emphasis on real‑time signal processing and communication systems.
Proven expertise in
RTL design (Verilog/SystemVerilog)
for high‑throughput, low‑latency digital receivers.
Proficient in integrating and validating
high‑speed serial interfaces
such as
LVDS, SPI, I2C, UART, and SERDES‑based links (e.g., JESD204, PCIe, Ethernet) .
Skilled in
FPGA synthesis, timing closure, and resource optimization
on platforms such as Xilinx or Intel/Altera.
Proficiency with simulation and verification tools (e.g., ModelSim, Questa, Vivado, VUnit) and scripting languages ( Python, Tcl ).
Understanding of
digital signal processing (DSP)
principles, including filtering, correlation, decimation, and fixed‑point arithmetic.
Ability to work closely with RF engineers, firmware developers, and systems engineers to integrate and validate end‑to‑end communication chains.
Demonstrated ability to work in a highly cross‑functional role.
Ability to work independently.
Strong interpersonal, verbal and written communication skills is a must.
Ability and willingness to thrive in a fast‑paced, rapidly changing work environment.
Passion for creating state‑of‑the‑art hardware systems.
STRONGLY DESIRED
Experience with
high‑speed memory interfaces , particularly
DDR/DDR3/DDR4 , including controller integration, timing constraints, and performance tuning.
Experience designing
distributed digital signal processing systems
across multiple FPGAs or compute nodes.
Familiarity with
soft‑core or hard‑core processor integration
(e.g., ARM) and peripheral interfacing (SPI, I2C, AXI).
Experience developing
packet decoders
for wireless communication protocols (e.g., BLE, ZigBee, LoRa, custom PHYs).
Familiarity with
synchronization techniques
(e.g., preamble detection, symbol timing recovery, frequency offset correction).
Experience working with
lab tools
such as oscilloscopes, logic analyzers, and RF test equipment for bring‑up and debugging.
Knowledge of
low‑power design techniques
for space‑based or resource‑constrained systems.
Familiarity with
BLE physical layer
characteristics or similar short‑range RF communication standards.
COMPENSATION & BENEFITS
Salary: $150,000.00 – $175,000.00 (commensurate with experience)
Comprehensive Benefits – Health, Dental, Vision, & HSA options
Unlimited PTO
Commuter Benefits
Learning & Development Allowance
Health & Wellness Stipend
Sabbatical Program – Recharge and explore new ideas
Cutting‑Edge Space Tech – Work on state‑of‑the‑art satellite system
ITAR REQUIREMENTS Hubble is required by the U.S. Government to comply with various space technology export regulations including the International Traffic in Arms Regulations (ITAR). All applicants must be a U.S. citizen, lawful permanent resident (“green card holder”) as defined by ITAR (22 CFR §120.15).
EEO STATEMENT Hubble is committed to creating a diverse environment and is proud to be an equal opportunity employer. Each individual has the right to work in a professional environment that promotes equal employment opportunity and prohibits discriminatory practices, including harassment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status.
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Hubble is an early-stage, venture-backed startup supported by some of the best investors in the world. In their previous lives, the founding team has been successful in raising $100s of millions in venture funding, developing the Amazon Sidewalk network, launching billions of dollars of space assets, and leading their teams to successful exits, both through acquisition and IPO. We are now looking to bring on talented team members who are the best at what they do to help us make Hubble a reality for the world.
Position Overview As a
Digital Design Engineer , you will play a key role in developing the RTL codebase for the FPGA module that performs localization and decodes packets from ground-based BLE device transmissions. You’ll collaborate closely with a cross‑functional team of system, hardware, and software engineers to optimize the throughput, accuracy, power efficiency, and reliability of the Hubble satellite constellation.
This is a full-time position based in Seattle, WA.
AN IDEAL CANDIDATE HAS
Sense of Urgency:
Lead projects from concept to reality, rapidly and effectively
First Principles Engineering:
Have a strong understanding of the whys behind the whats; have the ability to extrapolate from first principles to complex system design
High Learning Agility:
Love to learn; have a grounded approach to recognizing your weaknesses and take the initiative to brush up on and sharpen your engineering foundations to better collaborate with your teammates with different backgrounds
System‑Level Design and Analysis:
Understand the requirements flow down process and be able to quickly iterate on evolving requirements
Excellent Communication Skills:
Effectively convey ideas and communicate technical topics with engineering, build staff, and operations; run self‑directed design reviews and participate in reviews of parallel systems
Anticipation of Needs:
Identify problems, think creatively, and rapidly produce reliable and cost‑effective solutions to meet the ever growing and changing needs of an early‑stage company
BASIC QUALIFICATIONS
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
2-5 years of experience
in FPGA‑based digital design, with a strong emphasis on real‑time signal processing and communication systems.
Proven expertise in
RTL design (Verilog/SystemVerilog)
for high‑throughput, low‑latency digital receivers.
Proficient in integrating and validating
high‑speed serial interfaces
such as
LVDS, SPI, I2C, UART, and SERDES‑based links (e.g., JESD204, PCIe, Ethernet) .
Skilled in
FPGA synthesis, timing closure, and resource optimization
on platforms such as Xilinx or Intel/Altera.
Proficiency with simulation and verification tools (e.g., ModelSim, Questa, Vivado, VUnit) and scripting languages ( Python, Tcl ).
Understanding of
digital signal processing (DSP)
principles, including filtering, correlation, decimation, and fixed‑point arithmetic.
Ability to work closely with RF engineers, firmware developers, and systems engineers to integrate and validate end‑to‑end communication chains.
Demonstrated ability to work in a highly cross‑functional role.
Ability to work independently.
Strong interpersonal, verbal and written communication skills is a must.
Ability and willingness to thrive in a fast‑paced, rapidly changing work environment.
Passion for creating state‑of‑the‑art hardware systems.
STRONGLY DESIRED
Experience with
high‑speed memory interfaces , particularly
DDR/DDR3/DDR4 , including controller integration, timing constraints, and performance tuning.
Experience designing
distributed digital signal processing systems
across multiple FPGAs or compute nodes.
Familiarity with
soft‑core or hard‑core processor integration
(e.g., ARM) and peripheral interfacing (SPI, I2C, AXI).
Experience developing
packet decoders
for wireless communication protocols (e.g., BLE, ZigBee, LoRa, custom PHYs).
Familiarity with
synchronization techniques
(e.g., preamble detection, symbol timing recovery, frequency offset correction).
Experience working with
lab tools
such as oscilloscopes, logic analyzers, and RF test equipment for bring‑up and debugging.
Knowledge of
low‑power design techniques
for space‑based or resource‑constrained systems.
Familiarity with
BLE physical layer
characteristics or similar short‑range RF communication standards.
COMPENSATION & BENEFITS
Salary: $150,000.00 – $175,000.00 (commensurate with experience)
Comprehensive Benefits – Health, Dental, Vision, & HSA options
Unlimited PTO
Commuter Benefits
Learning & Development Allowance
Health & Wellness Stipend
Sabbatical Program – Recharge and explore new ideas
Cutting‑Edge Space Tech – Work on state‑of‑the‑art satellite system
ITAR REQUIREMENTS Hubble is required by the U.S. Government to comply with various space technology export regulations including the International Traffic in Arms Regulations (ITAR). All applicants must be a U.S. citizen, lawful permanent resident (“green card holder”) as defined by ITAR (22 CFR §120.15).
EEO STATEMENT Hubble is committed to creating a diverse environment and is proud to be an equal opportunity employer. Each individual has the right to work in a professional environment that promotes equal employment opportunity and prohibits discriminatory practices, including harassment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status.
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