Jobot
About the Role
Build next‑gen FPGA systems that power global connectivity. We’re hiring a Senior Digital Design Engineer to design high‑speed, low‑power signal processing hardware.
Responsibilities
Design, develop, and verify RTL code (Verilog/SystemVerilog) for real‑time digital signal processing systems.
Implement packet decoders and communication protocol logic (Bluetooth Low Energy, ZigBee, LoRa, or custom PHYs).
Integrate high‑speed memory interfaces (DDR/DDR3/DDR4) and serial interfaces (LVDS, SPI, I2C, UART, JESD204, PCIe, Ethernet).
Perform synthesis, timing closure, and resource optimization on FPGA platforms (Xilinx or Intel/Altera).
Collaborate with RF, firmware, and systems engineers to optimize end‑to‑end communication performance.
Conduct system‑level analysis and simulation to ensure signal integrity, throughput, and latency targets are met.
Develop testbenches, verification suites, and automation scripts (Python, Tcl).
Drive system‑level reviews and contribute to architecture decisions across hardware and embedded systems.
Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
5+ years of experience in FPGA design and real‑time signal processing.
Proficiency in Verilog/SystemVerilog, digital communication systems, and DSP fundamentals (filtering, correlation, fixed‑point arithmetic).
Experience with high‑speed memory and serial communication interfaces.
Strong background in FPGA synthesis, simulation, and performance optimization.
Familiarity with simulation and verification tools (ModelSim, Questa, Vivado, VUnit).
Skilled in scripting and automation (Python, Tcl).
Ability to work independently in a fast‑paced, collaborative engineering environment.
Excellent communication and cross‑functional collaboration skills.
Preferred experience: designing distributed DSP systems across multiple FPGAs or compute nodes.
Integration of soft‑core or hard‑core processors (ARM, RISC‑V) and embedded Linux environments (e.g., PetaLinux).
Experience with synchronization techniques (preamble detection, timing recovery, frequency offset correction).
Familiarity with lab instrumentation for validation and debugging (oscilloscopes, logic analyzers, RF tools).
Knowledge of low‑power digital design and space‑grade reliability techniques.
Understanding of short‑range RF communication standards such as Bluetooth Low Energy.
Benefits
Salary $150K – $180K (based on experience)
Comprehensive Health, Dental, Vision, HSA options
Unlimited PTO and flexible time off
Paid Parental Leave
Learning & Development Stipend
Wellness Support: monthly health & fitness allowance
Sabbatical Program: recharge and explore new ideas after five years
Cutting‑Edge Hardware: work on advanced digital and space‑based communication systems
Additional Perks: Team Offsites, Company Swag, And More
Equal Opportunity Statement Jobot is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates diversity and all qualified candidates receive consideration for employment without regard to race, color, sex, sexual orientation, gender identity, religion, national origin, age (40 and over), disability, military status, genetic information or any other basis protected by applicable federal, state, or local laws. Jobot also prohibits harassment of applicants or employees based on any of these protected categories. It is Jobot’s policy to comply with all applicable federal, state and local laws respecting consideration of unemployment status in making hiring decisions.
Background Check Policy Sometimes Jobot is required to perform background checks with your authorization. Jobot will consider qualified candidates with criminal histories in a manner consistent with any applicable federal, state, or local law regarding criminal backgrounds, including but not limited to the Los Angeles Fair Chance Initiative for Hiring and the San Francisco Fair Chance Ordinance.
Privacy Notice Information collected and processed as part of your Jobot candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Jobot’s Privacy Policy, as well as the Jobot California Worker Privacy Notice and Jobot Notice Regarding Automated Employment Decision Tools which are available at jobot.com/legal.
Contact & Application Interested in hearing more? Easy Apply now by clicking the “Easy Apply” button.
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Responsibilities
Design, develop, and verify RTL code (Verilog/SystemVerilog) for real‑time digital signal processing systems.
Implement packet decoders and communication protocol logic (Bluetooth Low Energy, ZigBee, LoRa, or custom PHYs).
Integrate high‑speed memory interfaces (DDR/DDR3/DDR4) and serial interfaces (LVDS, SPI, I2C, UART, JESD204, PCIe, Ethernet).
Perform synthesis, timing closure, and resource optimization on FPGA platforms (Xilinx or Intel/Altera).
Collaborate with RF, firmware, and systems engineers to optimize end‑to‑end communication performance.
Conduct system‑level analysis and simulation to ensure signal integrity, throughput, and latency targets are met.
Develop testbenches, verification suites, and automation scripts (Python, Tcl).
Drive system‑level reviews and contribute to architecture decisions across hardware and embedded systems.
Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
5+ years of experience in FPGA design and real‑time signal processing.
Proficiency in Verilog/SystemVerilog, digital communication systems, and DSP fundamentals (filtering, correlation, fixed‑point arithmetic).
Experience with high‑speed memory and serial communication interfaces.
Strong background in FPGA synthesis, simulation, and performance optimization.
Familiarity with simulation and verification tools (ModelSim, Questa, Vivado, VUnit).
Skilled in scripting and automation (Python, Tcl).
Ability to work independently in a fast‑paced, collaborative engineering environment.
Excellent communication and cross‑functional collaboration skills.
Preferred experience: designing distributed DSP systems across multiple FPGAs or compute nodes.
Integration of soft‑core or hard‑core processors (ARM, RISC‑V) and embedded Linux environments (e.g., PetaLinux).
Experience with synchronization techniques (preamble detection, timing recovery, frequency offset correction).
Familiarity with lab instrumentation for validation and debugging (oscilloscopes, logic analyzers, RF tools).
Knowledge of low‑power digital design and space‑grade reliability techniques.
Understanding of short‑range RF communication standards such as Bluetooth Low Energy.
Benefits
Salary $150K – $180K (based on experience)
Comprehensive Health, Dental, Vision, HSA options
Unlimited PTO and flexible time off
Paid Parental Leave
Learning & Development Stipend
Wellness Support: monthly health & fitness allowance
Sabbatical Program: recharge and explore new ideas after five years
Cutting‑Edge Hardware: work on advanced digital and space‑based communication systems
Additional Perks: Team Offsites, Company Swag, And More
Equal Opportunity Statement Jobot is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates diversity and all qualified candidates receive consideration for employment without regard to race, color, sex, sexual orientation, gender identity, religion, national origin, age (40 and over), disability, military status, genetic information or any other basis protected by applicable federal, state, or local laws. Jobot also prohibits harassment of applicants or employees based on any of these protected categories. It is Jobot’s policy to comply with all applicable federal, state and local laws respecting consideration of unemployment status in making hiring decisions.
Background Check Policy Sometimes Jobot is required to perform background checks with your authorization. Jobot will consider qualified candidates with criminal histories in a manner consistent with any applicable federal, state, or local law regarding criminal backgrounds, including but not limited to the Los Angeles Fair Chance Initiative for Hiring and the San Francisco Fair Chance Ordinance.
Privacy Notice Information collected and processed as part of your Jobot candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Jobot’s Privacy Policy, as well as the Jobot California Worker Privacy Notice and Jobot Notice Regarding Automated Employment Decision Tools which are available at jobot.com/legal.
Contact & Application Interested in hearing more? Easy Apply now by clicking the “Easy Apply” button.
#J-18808-Ljbffr