Senior DDR/LPDDR Validation Engineer – Onsite SJ

A technology firm in Santa Clara, CA, seeks a skilled engineer for onsite work who will validate memory interfaces and develop test plans. The ideal candidate has extensive expertise in platform level functional tests, FPGA experience, and proficiency in scripting languages like Python. This role offers a strong possibility of extension based on performance and requires clear communication skills and teamwork in a collaborative environment. #J-18808-Ljbffr