WinMax Systems Corporation
Principal Emulation and Validation Engineer
WinMax Systems Corporation, San Jose, California, United States, 95199
Principal Emulation and Validation Engineer
Full-time
Responsibilities
Synthesize complex system on chip designs and map into various hardware emulator platforms like Cadence Palladium or Mentor Veloce.
Develop system level tests using Tcl, iTcl, Python, C/C++ languages to verify networking switch chips and systems.
Create reusable design blocks, libraries and verification components for emulation.
Improve and define new verification / emulation methodologies.
Debug and resolve Pre / Post Silicon failures.
Create and maintain emulation environment for worldwide user community.
Write complex device driver using C/C++ to implement features on a flexible architecture and support and promote with wide range customer adoption.
Requirements
Total engineering minimum experience required is typically a BS degree and 12+ years of experience, an MS degree and 9+ years of experience or a PhD and 6 years of experience or equivalent.
BS (EE/Electrical Engineering or CS/Computer Science) required; MS (EE or CS) preferred or equivalent.
Hands‑on experience with leadership qualities on driving ASIC / SoC verification flows and methodologies.
Must have hands‑on experience with network protocol validation, RFC, IEEE, etc.
Good knowledge of languages relevant to the ASIC verification process including Verilog, System Verilog, Tcl, iTcl, Perl, Python, Ruby, C/C++ and Unix Scripting.
Strong expertise in writing system‑level tests and drivers using C/C++, Tcl, iTcl, Perl and Python.
Excellent structured programming skills, data structures, algorithms, SCM for large complex SW projects; automation experience is a plus.
Strong Pre/Post Silicon debugging, analytical and independent problem‑solving ability.
Good knowledge of using industry‑standard debugging tools for both HW & SW.
Must be a team player with good verbal and written communication skills.
Must be self‑driven engineer with good project management and organizational skills to deliver high‑quality output in a timely manner.
All your information will be kept confidential according to EEO guidelines.
#J-18808-Ljbffr
Responsibilities
Synthesize complex system on chip designs and map into various hardware emulator platforms like Cadence Palladium or Mentor Veloce.
Develop system level tests using Tcl, iTcl, Python, C/C++ languages to verify networking switch chips and systems.
Create reusable design blocks, libraries and verification components for emulation.
Improve and define new verification / emulation methodologies.
Debug and resolve Pre / Post Silicon failures.
Create and maintain emulation environment for worldwide user community.
Write complex device driver using C/C++ to implement features on a flexible architecture and support and promote with wide range customer adoption.
Requirements
Total engineering minimum experience required is typically a BS degree and 12+ years of experience, an MS degree and 9+ years of experience or a PhD and 6 years of experience or equivalent.
BS (EE/Electrical Engineering or CS/Computer Science) required; MS (EE or CS) preferred or equivalent.
Hands‑on experience with leadership qualities on driving ASIC / SoC verification flows and methodologies.
Must have hands‑on experience with network protocol validation, RFC, IEEE, etc.
Good knowledge of languages relevant to the ASIC verification process including Verilog, System Verilog, Tcl, iTcl, Perl, Python, Ruby, C/C++ and Unix Scripting.
Strong expertise in writing system‑level tests and drivers using C/C++, Tcl, iTcl, Perl and Python.
Excellent structured programming skills, data structures, algorithms, SCM for large complex SW projects; automation experience is a plus.
Strong Pre/Post Silicon debugging, analytical and independent problem‑solving ability.
Good knowledge of using industry‑standard debugging tools for both HW & SW.
Must be a team player with good verbal and written communication skills.
Must be self‑driven engineer with good project management and organizational skills to deliver high‑quality output in a timely manner.
All your information will be kept confidential according to EEO guidelines.
#J-18808-Ljbffr