FPGA Verification Engineer: UVM, SystemVerilog & Debugging

A leading technology firm seeks a skilled FPGA Verification Engineer in Mountain View. This role involves verifying FPGA designs with advanced methodologies and requires strong expertise in SystemVerilog, UVM, and debugging skills. The ideal candidate will develop verification plans, utilize industry-standard tools, and collaborate with cross-functional teams to enhance product quality. Competitive compensation is offered. #J-18808-Ljbffr