Remote FPGA Verification Engineer - UVM/SystemVerilog

A leading tech solutions provider is seeking an experienced FPGA Design Verification Engineer to join their team. You will be responsible for verifying complex FPGA designs, working closely with engineers, and utilizing industry-standard methodologies. The ideal candidate has over 10 years of FPGA experience and strong skills in System Verilog and UVM. This role is remote, offering a competitive salary range of $101,000-$152,000 with comprehensive benefits. #J-18808-Ljbffr