SoC RTL Design Engineer — SystemVerilog & ASIC Innovation

A world-leading technology company in San Francisco is looking for an experienced RTL Design Engineer to translate architectural specifications into robust RTL designs. The ideal candidate has a B.Sc./M.Sc. in Electrical Engineering or a related field, with over 3 years in ASIC/SoC projects and a strong proficiency in SystemVerilog. This role offers the opportunity to impact next-generation semiconductor innovations while collaborating with cross-functional teams. #J-18808-Ljbffr