Senior AI Hardware ASIC RTL Design Engineer

A leading electric vehicle manufacturer is seeking a Senior ASIC RTL Design Engineer for its AI Hardware team in Palo Alto, CA. The role involves microarchitecture design and delivering efficient RTL designs for high-performance AI accelerators. Candidates should have over 5 years of industry experience, a degree in Electrical Engineering or Computer Science, and expertise in Verilog design. The position offers competitive compensation and a range of benefits, reflecting the company's commitment to employee well-being. #J-18808-Ljbffr