Senior ASIC RTL Design Engineer for AI Accelerators

A leading automotive and energy company is seeking a Senior ASIC RTL Design Engineer with a focus on AI hardware in Palo Alto, CA. The ideal candidate will have 5+ years of experience and expertise in high-performance RTL design techniques. Responsibilities include developing micro-architecture specifications, collaborating with cross-functional teams, and ensuring efficient design. The role offers a competitive salary range of $120,000 to $264,000 along with comprehensive benefits, making it an attractive opportunity for qualified candidates. #J-18808-Ljbffr