ADPMN Inc
Job Title
FPGA/Design Verification Engineer
Location Mountain View, CA (Onsite)
Duration 12+ Months
Job Description
Strong understanding of FPGA design principles and architecture.
Proficiency in System Verilog and UVM verification methodology.
Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).
Knowledge of code coverage and functional coverage analysis.
Excellent debugging and problem-solving skills.
Strong communication and collaboration skills.
Requirements
Bachelors or masters degree in electrical engineering, Computer Engineering, or a related field.
Experience in FPGA verification.
Experience with scripting languages (e.g., Python, Perl).
Familiarity with hardware description languages (e.g., VHDL, Verilog).
Seniority level Entry level
Employment type Full-time
Job function Engineering and Information Technology
Industries IT Services and IT Consulting
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Location Mountain View, CA (Onsite)
Duration 12+ Months
Job Description
Strong understanding of FPGA design principles and architecture.
Proficiency in System Verilog and UVM verification methodology.
Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).
Knowledge of code coverage and functional coverage analysis.
Excellent debugging and problem-solving skills.
Strong communication and collaboration skills.
Requirements
Bachelors or masters degree in electrical engineering, Computer Engineering, or a related field.
Experience in FPGA verification.
Experience with scripting languages (e.g., Python, Perl).
Familiarity with hardware description languages (e.g., VHDL, Verilog).
Seniority level Entry level
Employment type Full-time
Job function Engineering and Information Technology
Industries IT Services and IT Consulting
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