Dexian
Mixed Signal Model Verification Engineer
San Jose, CA (Hybrid)
3 + Months
$90-95/HR
Goal Verify SystemVerilog (logic/real number) behavioral models against custom circuit schematics using formal equivalence checking and co-simulation.
Requirements
SystemVerilog Modeling: Extensive experience with SystemVerilog, including real number modeling.
Verification Flow: Strong understanding of HDL/SPICE co-simulations.
Circuit Expertise: Strong background in analog integrated circuit design and reading custom circuit schematics.
Tools: Experience with formal equivalence checking tools (e.g., ESP).
Dexian is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.
To learn more, please visit https://dexian.com/.
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Goal Verify SystemVerilog (logic/real number) behavioral models against custom circuit schematics using formal equivalence checking and co-simulation.
Requirements
SystemVerilog Modeling: Extensive experience with SystemVerilog, including real number modeling.
Verification Flow: Strong understanding of HDL/SPICE co-simulations.
Circuit Expertise: Strong background in analog integrated circuit design and reading custom circuit schematics.
Tools: Experience with formal equivalence checking tools (e.g., ESP).
Dexian is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.
To learn more, please visit https://dexian.com/.
#J-18808-Ljbffr