Hybrid Mixed-Signal Verification Engineer (SystemVerilog)

A technology solutions provider in California is looking for a Mixed Signal Model Verification Engineer to verify SystemVerilog behavioral models against custom circuit schematics using formal equivalence checking and co-simulation. Strong experience in SystemVerilog and analog integrated circuits is required for this role. The position offers a hybrid work model with a pay rate between $90 and $95 per hour. #J-18808-Ljbffr