Hybrid Mixed-Signal Model Verifier (SystemVerilog/Analog)

A leading technology solutions firm in California seeks a Mixed Signal Model Verification Engineer for a hybrid role. The ideal candidate will verify SystemVerilog behavioral models against analog circuit schematics and have extensive experience in real number modeling and HDL/SPICE co-simulations. Experience with formal equivalence checking tools is essential. This contract position offers competitive compensation of $90-95/hr for a duration of 3+ months. #J-18808-Ljbffr