Senior ASIC Physical Design Engineer - CTS/Timing

A leading tech company is seeking a HW SOC/ASIC Physical Design Engineer for its Boulder, CO location. You will execute floorplanning and drive timing closure while collaborating closely with RTL designers. This role requires a Bachelor's or Master's degree in Electrical Engineering and 4+ years of relevant experience. The company offers benefits and a pay range of $140,000 to $210,000 annually, along with an annual bonus program and RSU grants. #J-18808-Ljbffr