Tech Providers,
Verify behavioral models written in SystemVerilog (logic + RNM) for mixed-signal IP
Write constraints and stimuli for CAD tools to perform schematic vs. model equivalence checks
Debug mismatches between behavioral models and transistor-level implementations
Analyze and interpret mixed-signal schematics to understand intended circuit functionality
Modify or refine behavioral models to achieve full functional equivalence
Collaborate with analog designers and CAD teams to ensure modeling accuracy and verification closure
#J-18808-Ljbffr
Write constraints and stimuli for CAD tools to perform schematic vs. model equivalence checks
Debug mismatches between behavioral models and transistor-level implementations
Analyze and interpret mixed-signal schematics to understand intended circuit functionality
Modify or refine behavioral models to achieve full functional equivalence
Collaborate with analog designers and CAD teams to ensure modeling accuracy and verification closure
#J-18808-Ljbffr