SystemVerilog Mixed-Signal Verification Engineer

A technology company in the United States is seeking a specialized candidate to verify and refine behavioral models focusing on mixed-signal IP. The position requires collaboration with analog designers and CAD teams to ensure accuracy and functional equivalence in modeling. Responsibilities include debugging mismatches, writing constraints for CAD tools, and analyzing schematics to understand circuit functionality. The ideal candidate will have experience in SystemVerilog and mixed-signal verification. #J-18808-Ljbffr