Senior SV/UVM Verification Engineer

A leading technology company is looking for a Verification Engineer specializing in SystemVerilog and UVM in San Diego. The role involves developing verification environments, executing regression runs, and collaborating with teams across design and validation. The ideal candidate has a strong understanding of SystemVerilog, UVM, and AMBA protocols, with the ability to enhance verification processes. This full-time position offers a competitive salary range of $145,000 to $175,000 per year. #J-18808-Ljbffr