Cadence Design Systems
Lead C++ Engineer — FPGA Prototyping & QoR Optimizations
Cadence Design Systems, San Jose, California, United States, 95199
A leading technology company in California is seeking an exceptional C++ Software Engineer to develop and enhance their FPGA-based prototyping product. The role includes implementing algorithms, developing EDA automation, and writing design specifications. Ideal candidates will have a degree in Computer Science or related fields and significant C/C++ experience. The position offers a competitive salary range from $110,600 to $205,400, along with various benefits including a 401(k) plan and paid vacations.
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